SPHE8281D ETC-unknow, SPHE8281D Datasheet
SPHE8281D
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SPHE8281D Summary of contents
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Sunplus Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Technology is believed to be accurate and reliable. However, Sunplus Technology makes no warranty for any errors which ...
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... Video timing diagrams ................................................................................................................................................................. 31 7. PACKAGE/PAD LOCATION .......................................................................................................................................................................... 33 7. ............................................................................................................................................................................... 33 UTLINE IMENSIONS 8. DISCLAIMER .................................................................................................................................................................................................. 34 9. REVISION HISTORY ...................................................................................................................................................................................... 35 © Sunplus Confidential Contents are subject to change without Notice Table of Contents ..................................................................................................................................................... 22 ........................................................................................................................................................... SPHE8281D/Dx PAGE MAY. 19, 2005 Preliminary Version: 0.1 ...
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... DVD SINGLE CHIP MPEG A/V PROCESSOR 1.GENERAL DESCRIPTION SPHE8281D A/V decoder is a single-chip integrated DVD A/V decoder designed to maximize system performance with minimum cost. It integrates DVD/CD controller, host processor, A/V decoding hardware, audio quality DAC and a 6-channel multi-format TV-encoder. SPHE8281D supports DVD and CD physical formats. For logical formats it supports DVD-Video, Super Video CD, Video CD, CD-DA, OKO, and CD-ROM discs ...
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... Technology — Advanced CMOS technology — 216-pin LQFP package — 3v (I/O) and 1.8v (kernel) power supplies — 5v I/O tolerance 3 Macrovision is a trademark of Macrovision Corporation SPHE8281D/ 7.1.D1 and Macrovision AGC v1.03 MAY. 19, 2005 Preliminary Version: 0 ...
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... Licensing Notice In order to take care of different royalties, Sunplus SPHE8281D series have different combinations for different royalties. For detail information, please contact with Sunplus Sales. Supply of the implementation of Dolby, WMA, Macrovision … technologies do not imply of a right or convey a license under any patent, or any Intellectual Property Right of each respective company ...
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... RISC Power control icache dcache Audio DSP Intr. control Timer icache mem RISC DMA Bootstrap HOST DMA OSD decoder Sub-picture decoder MPEG video Video post- decoder processing Figure 3-1 SPHE8281D block diagram ...
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... RF_AVDD 210 GMRES 211 AGCCAP 212 RFRP 213 RFO 214 FLTIP 215 FLTIN 216 © Sunplus Confidential Contents are subject to change without Notice SPHE8281D 8202D-216P 216 PIN LQFP 2 24x24mm Figure 4-1 SPHE8281D pin ...
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... RFRPPH RFRPBH RFRPMEAN M_BA0 M_BA1 M_A11 M_A[10:0] M_D[15:0] M_DQM[3:0] IR_IN VFD_CLK VFD_STB VFD_DATA UA0_RX UA0_TX Other GPIOs V_COMP V_BIAS V_FSADJ V_REFOUT V_DAC0 V_DAC3 V_DAC4 V_DAC5 Figure 4-2 SPHE8281D pin groups SPHE8281D/Dx LPFO LPFN VREFO PDFLT FDFLT LPFNIN LGIN ...
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... Sub-beam adds signal output. Focus error signal output. Tracking error signal output. I Op-amp 1 positive input. I Op-amp 1 negative input. Op-amp output. Servo/ADC analog ground Servo ADC/DAC 3.3V power SPHE8281D/Dx Description MAY. 19, 2005 Preliminary Version: 0 ...
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... Priority selection sft_cfg2[11:10]=2’b01,2’b10 AT_DIOW_B sft_cfg4[2]=1’b1 SC1_OUT (default) Sft_cfg8[9]=1’b1 DAC_PDD sft_cfg8[8]=1’b1 OTP_TEST_ADDR[2] (other) GPIO[ SPHE8281D/Dx Function Dir I/O I/O I I/O Function dir I/O I/O I I/O Function dir O I I/O Function dir O I/O ...
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... DSP_FL1 Sft_cfg8[9]=1’b1 DAC_DATA_F[8] sft_cfg7[15:14]=2’b11 CLK27_OUT sft_cfg9[14:13]=2’b10 EXT_CLK48 sft_cfg6[4]=1’b1 DELAY_CHAIN2 (other) GPIO[7] (default SPHE8281D/Dx Function dir I I I/O Function dir I/O Function dir I/O Function dir ...
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... RISC_INT1_12 Sft_cfg3[11:10]=2’b01 ADC_LRCK, digital audio input interface L/R strobe fm_gpio_len[3:0] > 0 FM_GPIOB[3] Sft_cfg8[9]=1’b1 DAC_DATA_F[3] (other) GPIO[12] (default SPHE8281D/Dx Function dir I/O Function dir O O I/O I I/O Function dir O O I/O I I/O Function dir O I/O I I/O I/O I I/O Function ...
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... ROM / SRAM / flash chip select #4 or GPIO Priority selection sft_cfg1[3]=1’b1 R_CS4_B (default) sft_cfg1[7]=1’b1 & FM_GPIOB[20] fm_gpio_len[3:0] = 10,11,12 sft_cfg8[9]=1’b1 DAC_DATA_E[9] (other) GPIO[16 SPHE8281D/Dx Function dir O I I/O I I/O Function dir I I/O I I/O Function dir I ...
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... Ground pin for system PLL and audio PLL 1.8V power supply pin for system PLL SDRAM data bus [7] SDRAM data bus [6] SDRAM data bus [5] SDRAM data bus [ SPHE8281D/Dx Description Function dir R_CS3_B (default) O DAC_DATA_E[8] I GPIO[17] I/O Function dir R_CS2_B (default) O DAC_DATA_E[7] I GPIO[18] I/O Function ...
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... GPIO[26] SDRAM address bus [9] SDRAM address bus [8] SDRAM address bus [7] SDRAM address bus [6] SDRAM address bus [ SPHE8281D/Dx Function dir O I I/O Function dir O I I/O Function dir O I I/O MAY. 19, 2005 Preliminary Version: 0 ...
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... ROM / SRAM / flash address bus bit [8] ROM / SRAM / flash address bus bit [9] ROM / SRAM / flash address bus bit [11] ROM / SRAM / flash address bus bit [10 SPHE8281D/Dx Function dir I I/O Function dir I I/O MAY. 19, 2005 Preliminary Version: 0 ...
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... ROM / SRAM / flash data bus bit [5] ROM / SRAM / flash data bus bit [4] ROM / SRAM / flash data bus bit [3] Kernel logic / I/O power shared ground supply # SPHE8281D/Dx Function dir I I I/O Function dir ...
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... Serial audio data output for channel 3/2 or GPIO Priority selection sft_cfg3[2]=1’b1 A_DATA[1] (default) sft_cfg8[8]=1’b1 ADC_MONO_C[2] sft_cfg8[9]=1’b1 DAC_OPF[2] (other) GPIO[54 SPHE8281D/Dx Function Dir I/O Function Dir I/O Function Dir I/O MAY. 19, 2005 Preliminary Version: 0 ...
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... UART #0 data receive or GPIO Priority selection sft_cfg2[3:2] =2’b01 UART0_RX (default) sft_cfg3[13:12]=2’b01 TV_HSYNC sft_cfg4[15:13]=3’b011 HSYNC_PC (other) GPIO[60 SPHE8281D/Dx Function Dir I/O Function Dir I/O Function dir I I/O Function Dir I I/O Function Dir I/O I ...
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... Servo PLL 3.3V power NC pin NC pin Servo PLL/Data-slicer ground Servo Data slicer 3.3V power Servo RF 3.3V power External reference resistor input. External AGC capacitor connected to ground SPHE8281D/Dx Function Dir O I/O O I/O MAY. 19, 2005 Preliminary Version: 0 ...
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... Note: Please reference SPHE802D servo datasheet for servo related information. © Sunplus Confidential Contents are subject to change without Notice RFRP signal output. RF signal output. I Differential RF equalizer input #P I Differential RF equalizer input # SPHE8281D/Dx Description MAY. 19, 2005 Preliminary Version: 0 ...
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... Sunplus Confidential Contents are subject to change without Notice Module-level stop-operation: SPHE8281D provides a function to turn off specific module from operating. Without explicit wake-up, the hardware module will remain static and consume little power. System-level doze: For maximum power-saving, firmware could fine-tune system performance according to system task ...
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... INT_EXT3 INT_IOP INT_AUD 5.4. ROM/Flash/SRAM Controller The SPHE8281D provides flexible connections to external ROM, Flash or SRAM (RFS). It can support external RFS devices by using different chip-selects (R_CS_B[3:0]). The firmware can configure RFS memory anchor registers and map these devices into locations of RISC memory space. For each memory space it can be in flash mode or in ISA mode ...
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... DATA[] Data (read) data is sampled at this point Figure 5-6 ISA mode timing 5.5. CSS Decryption Hardware (Optional) SPHE8281D has built-in CSS decryption hardware DMA support. 5.6. MPEG Video Decoder The system incorporates a powerful MPEG video decoding datapath and provides real-time video decoding of MPEGI/II bitstream. ...
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... It supports real-time vertical expansion for PAL/NTSC translation or special effect. 5.14. On Screen Display IEC-958 input The on screen display (OSD) function of the SPHE8281D provides digital audio input an overlay bitmap graphics on the final TV display. Applications can use this function to display specific information over the video ...
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... Half current, quarter current modes are provided for low power operation using external current amplifiers. 5.17. GPIO In SPHE8281D almost every pin that related to selectable features can serve as general-purpose input-output (GPIO) control function. OSD When a pin is programmed to this mode, the RISC controller or ...
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... DDIO Symbol Min. Typ 3 3.5 OUT C - 3.5 BIDIR SPHE8281D/Dx Unit C C mA Max. Units 1.90 V 3.45 V 5 Max. Units - MAY. 19, 2005 Preliminary Version: 0.1 ...
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... HIGH CAb tBDL DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 Write Burat Stop (A-Bank SPHE8281D/ tCCD RAc CAc RAc *Note 1 tCDL DBb1 DBb2 DBb3 CAc0 CAc1 CAc2 DBb1 DBb2 DBb3 CAc0 CAc1 ...
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... ACCESS SPHE8281D/Dx Typ. Max. Units 2 4 System clock cycle * System clock cycle * System clock cycle * System clock cycle * System clock cycle * System clock cycle ...
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... Figure 6-3 Normal mode / 24bit data / 24bit frame / MSB first left channel MSB LSB SPHE8281D/Dx t ACCESS Address (write) t WEH WAIT OH IH Data (write) Typ. Max. Units - 31 System clock cycle - 1000 System clock cycle - - ns ...
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... V blanking period (21) Figure 6-8 NTSC (480i) timing diagram SPHE8281D/ right channel right channel right channel 22 21 ...
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... Figure 6-10 NTSC (480p) timing diagram 623 624 625 Figure 6-11 PAL (576p) timing diagram SPHE8281D/Dx SP active period active line period 328 329 330 331 332 333 334 335 ...
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... BSC. 24.00 BSC. 24.00 BSC. 26.00 BSC. 26.00 BSC. 24.00 BSC. 24.00 BSC. 0. 0.09 - 0.45 0.60 1.00 REF 1.00 REF 0. SPHE8281D/ Max. 1.60 0.15 1.45 26.00 BSC. 24.00 BSC. 26.00 BSC. 24.00 BSC. 0. 0.20 0.75 1.00 REF - MAY. 19, 2005 Preliminary Version: 0 ...
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... SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Confidential Contents are subject to change without Notice SPHE8281D/ ...
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... HISTORY Date Revision # MAY. 19, 2005 0.1 Original © Sunplus Confidential Contents are subject to change without Notice SPHE8281D/Dx Description Page 35 MAY. 19, 2005 Preliminary Version: 0.1 ...