AX88796L Asix, AX88796L Datasheet
AX88796L
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AX88796L Summary of contents
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... Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ...
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... Test Register (TR) Offset 15H (Read) ..........................................................................................................38 5.1.15 General Purpose Input Register (GPI) Offset 17H (Read) ..........................................................................38 3-in-1 Local Bus Fast Ethernet Controller CONTENTS ...................................................................................................................6 IAGRAM SPP P O ............................................................................7 IAGRAM WITH ORT PTION G .......................................................................................................12 IGNALS ROUP ..............................................................................................13 .......................................................................................................... ..........................................................................................................14 PTIONAL (O NTERFACE PINS GROUP PTIONAL PINS GROUP ................................................................................................15 .................................................................................................................................16 ................................................................................................................................18 ........................................................................................................................ ..................................................................15 .......................17 ASIX ELECTRONICS CORPORATION ...
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... APPENDIX A: APPLICATION NOTE 1...................................................................................................................63 A 25MH SING RYSTAL A SING SCILLATOR APPENDIX B: POWER CONSUMPTION REFERENCE DATA ..........................................................................64 ERRATA OF AX88796..................................................................................................................................................65 DEMONSTRATION CIRCUIT (A) : AX88796 WITH ISA BUS + HOMEPNA 1M8 PHY.................................66 3-in-1 Local Bus Fast Ethernet Controller ...........................................................................................................................40 . .........................................................................................................................51 ..............................................................................................................51 ...........................................................................................................52 . .........................................................................................................52 ..........................................................................................53 ANAGEMENT FUNCTIONS ..............................................................................................................................54 ........................................................................................................................54 .............................................................................................................................55 Z ......................................................................................................................63 25MH Z ...............................................................................................................63 3 ASIX ELECTRONICS CORPORATION ...
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... IAGRAM FOR US ODE ......................................................................................9 IAGRAM FOR X ODE MC68K M .................................................................................10 IAGRAM FOR ODE MCS-51 M .................................................................................11 IAGRAM FOR ODE ...........................................................................................................23 TABLES ......................................................................................................12 I .........................................................................................13 NTERFACES PINS GROUP .......................................................................................................13 ..........................................................................................................14 ..........................................................................................................................14 ..............................................................................................15 ...................................................................................................................15 .............................................................................................................................. ..........................................................................................................17 ETUP ABLE ................................................................................................................................18 M ....................................................................................................32 APPING M ....................................................................................................33 APPING ......................................................................................................................40 F .................................................................................................................53 ORMAT - D .............................................................................................53 FIELD ESCRIPTION 4 ASIX ELECTRONICS CORPORATION ...
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... GPIO Print Port or General I/O Fig - 1 AX88796 Block Diagram 3-in-1 Local Bus Fast Ethernet Controller 8K* 16 SRAM and Memory Arbiter I/F Remote DMA NE2000 FIFOs Registers Host Interface Ctl BUS SA[9:0] 5 SMDC SMDIO STA TPI, TPO MAC Core & PHY+ MII I/F Tranceiver SD[15:0] ASIX ELECTRONICS CORPORATION ...
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... Fig - 2 AX88796 Pin Connection Diagram 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus Controller VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] 59 CPU[0] 58 VDD 57 VDDA 56 VSSA 55 VSS 54 VDD 53 VSS 52 EECS 51 EECK 50 EEDI 49 EEDO 48 TEST2 47 IDDQ 46 BIST 45 CLKO25M 44 VSS 43 SD[0] 42 SD[1] 41 VDD 40 SD[2] 39 ASIX ELECTRONICS CORPORATION ...
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... Local Bus Fast Ethernet Controller AX88796 Local CPU Bus Controller (With SPP Port VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] 59 CPU[0] 58 VDD 57 VDDA 56 VSSA 55 54 VSS VDD 53 VSS 52 EECS 51 EECK 50 EEDI 49 EEDO 48 TEST2 47 IDDQ 46 BIST 45 CLKO25M 44 VSS 43 SD[0] 42 SD[1] 41 VDD 40 SD[2] 39 ASIX ELECTRONICS CORPORATION ...
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... Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller (for ISA Bus I/ VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] 59 CPU[0] 58 VDD 57 VDDA 56 VSSA 55 VSS 54 VDD 53 VSS 52 EECS 51 EECK 50 EEDI 49 EEDO 48 TEST2 47 IDDQ 46 BIST 45 CLKO25M 44 VSS 43 SD[0] 42 SD[1] 41 VDD 40 SD[2] 39 ASIX ELECTRONICS CORPORATION ...
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... Fig - 5 AX88796 Pin Connection Diagram for 80x86 Mode 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] 59 CPU[0] 58 VDD 57 VDDA 56 VSSA 55 VSS 54 VDD 53 VSS 52 EECS 51 EECK 50 EEDI 49 EEDO 48 TEST2 47 IDDQ 46 BIST 45 CLKO25M 44 VSS 43 SD[0] 42 SD[1] 41 VDD 40 SD[2] 39 ASIX ELECTRONICS CORPORATION ...
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... Fig - 6 AX88796 Pin Connection Diagram for MC68K Mode 3-in-1 Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] 59 CPU[0] 58 VDD 57 VDDA 56 VSSA 55 VSS 54 VDD 53 VSS 52 EECS 51 EECK 50 EEDI 49 EEDO 48 TEST2 47 IDDQ 46 BIST 45 CLKO25M 44 VSS 43 SD[0] 42 SD[1] 41 VDD 40 SD[2] 39 ASIX ELECTRONICS CORPORATION ...
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... Local Bus Fast Ethernet Controller AX88796 Local CPU Bus 10/100BASE-TX MAC Controller VSS 63 I_ACT 62 I_SPEED 61 I_LINK 60 CPU[1] 59 CPU[0] 58 VDD 57 VDDA 56 VSSA 55 54 VSS VDD 53 VSS 52 EECS 51 EECK 50 EEDI 49 EEDO 48 TEST2 47 IDDQ 46 BIST 45 CLKO25M 44 VSS 43 SD[0] 42 SD[1] 41 VDD 40 SD[2] 39 ASIX ELECTRONICS CORPORATION ...
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... I/O command. PSEN : This signal is active low for 8051 program access. For I/O device, AX88796, this signal is active high to access the chip. This signal is for 8051 bus application only. 12 Pull Up Pull Down Power Pin DESCRIPTION ASIX ELECTRONICS CORPORATION ...
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... Link Status/Active : When I_OP is logic 0. If this signal is low, it indicates link, and high, then the link is fail. When in link status and line activity occurrence, the output will be driven low for 0.67 sec and driven high at least 0.67 sec. (Current sink capacity is 6mA) 13 ASIX ELECTRONICS CORPORATION ...
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... Station Management Data Input/Output :Serial data input/output transfers from/to the PHYs . The transfer protocol has to meet the IEEE 802.3u MII specification. For more information, please refer to section 6.5 CPU Access MII Station Management functions. 14 DESCRIPTION DESCRIPTION ASIX ELECTRONICS CORPORATION ...
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... When MII port is selected. Read register offset 17h bit 4 value reflects this input value. When SPP port is selected. The pin is defined as SLCT. 120 Default “1”. The pin reflects write register offset 17h bit 0 inverted value. 15 DESCRIPTION Description ASIX ELECTRONICS CORPORATION ...
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... No Connection : for manufacturing test only. 125 Power Supply : +3.3V DC. Power Supply : + Ground Power. 127 Power Supply for Analog Circuit: +3.3V DC. 16 DESCRIPTION CPU TYPE ISA BUS 80186 MC68K MCS-51 (805X) IO_BASE 0 300h 1 320h 0 340h 1 360h 0 380h 1 3A0h 0 200h(default) 1 220h ASIX ELECTRONICS CORPORATION ...
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... Power Supply for Transceiver Output Driver: +3.3V DC. Power Supply for Transceiver Output Driver: + Ground. Description Standard Printer Port Selection: /SPP_SET = 0 : Standard Printer Port or GPIO is selected /SPP_SET = 1 : MII port is selected (default) PPD_SET = 0 : Internal PHY in normal mode. (default) PPD_SET = 1 : Internal PHY in power down mode. 17 ASIX ELECTRONICS CORPORATION ...
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... SYSTEM I/O OFFSET 0000H 001FH Tab - 10 I/O Address Mapping 3.3 SRAM Memory Mapping OFFSET 0000H 3FFFH 4000H 7FFF 8000H FFFFH Tab - 11 Local Memory Mapping 3-in-1 Local Bus Fast Ethernet Controller FUNCTION MAC CORE REGISTER FUNCTION RESERVED NE2000 COMPATABLE MODE SRAM BUFFER RESERVED 18 ASIX ELECTRONICS CORPORATION ...
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... FB12 FB11 FB21 FB20 FB19 FB29 FB28 FB27 FB37 FB36 FB35 FB45 FB44 FB43 FB53 FB52 FB51 FB61 FB60 FB59 19 ASIX ELECTRONICS CORPORATION DA2 DA1 DA0 DA10 DA9 DA8 DA18 DA17 DA16 DA26 DA25 DA24 DA34 DA33 DA32 DA42 DA41 ...
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... Bro =1 Brocast Address Match =0 Brocast Address not Match AGG =1 Aggregate Address Match =0 Aggregate Address not Match The meaning of AB, AM and PRO signals, please refer to “ 3-in-1 Local Bus Fast Ethernet Controller Selected bit 0 = reject, 1= accept Receive Configuration Register” 20 ASIX ELECTRONICS CORPORATION ...
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... AX88796 L Aggregate Address Filter function will be: Bro AND Logic AB /Bro /Mul AND Logic PRO /Bro Mul AND Logic AM Phy 3-in-1 Local Bus Fast Ethernet Controller OR Logic 21 ASIX ELECTRONICS CORPORATION AGG ...
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... DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address. Page Start Buffer #1 Buffer #2 Buffer #3 … … … … Buffer #n Page Stop Physical Memory Map Fig - 8 Receive Buffer Ring 3-in-1 Local Bus Fast Ethernet Controller 4000h … n-2 n-1 8000h Logic Receive Buffer Ring 22 ASIX ELECTRONICS CORPORATION ...
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... When linking buffers, buffer management will never cross this pointer, effectively avoiding any overwrites. If the buffer address does not match either the Boundary Pointer or Page Stop Address, the link to the next buffer is performed. 3-in-1 Local Bus Fast Ethernet Controller 4000h … n-2 n-1 8000h Logic Receive Buffer Ring 23 ASIX ELECTRONICS CORPORATION ...
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... If the ``Resend'' variable is set reset the ``Resend'' variable and reissue the transmit command. This is done by writing a value of 26H to the Command Register. If the ``Resend'' variable is 0, nothing needs to bedone. END OF PACKET OPERATIONS 3-in-1 Local Bus Fast Ethernet Controller 24 ASIX ELECTRONICS CORPORATION ...
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... The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796 Controller is set in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and setting the pins for ISA, 80186 or MC68K mode. CPU[1:0] 3-in-1 Local Bus Fast Ethernet Controller 25 ASIX ELECTRONICS CORPORATION ...
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... BOS = 0, WTS = 1 in Data Configuration Register. This format is used with ISA or 80186 Mode. 3-in-1 Local Bus Fast Ethernet Controller 6 Bytes 6 Bytes 2 Bytes 46 Bytes Min Destination Address 0 Destination Address 2 Destination Address 4 Source Address 0 Source Address 2 Source Address 4 Type / Length 0 Data 1 Data 0 … … ASIX ELECTRONICS CORPORATION ...
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... Destination Address 2 (DA2) Destination Address 3 (DA3) Destination Address 4 (DA4) Destination Address 5 (DA5) Source Address 0 (SA0) Source Address 1 (SA1) Source Address 2 (SA2) Source Address 3 (SA3) Source Address 4 (SA4) Source Address 5 (SA5) Type / Length 0 Type / Length 1 Data 0 Data 1 … ASIX ELECTRONICS CORPORATION ...
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... The following diagrams describe the format for how received packets are placed into memory by the local DMA channel. These modes are selected in the Data Configuration Register and setting the ISA, 80186, MC68K or MCS-51 mode. D15 3-in-1 Local Bus Fast Ethernet Controller ASIX ELECTRONICS CORPORATION pins for CPU[1:0] D0 ...
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... Destination Address 4 Source Address 0 Source Address 2 Source Address 4 Type / Length 0 Data 0 … Next Packet Pointer Receive Byte Count 1 Destination Address 1 Destination Address 3 Destination Address 5 Source Address 1 Source Address 3 Source Address 5 Type / Length 1 Data 1 … Receive Status 29 ASIX ELECTRONICS CORPORATION D0 D0 ...
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... Destination Address 3 Destination Address 4 Destination Address 5 Source Address 0 Source Address 1 Source Address 2 Source Address 3 Source Address 4 Source Address 5 BOS = 0, WTS = 0 in Data Configuration Register. This format is used with ISA, 80186 or MCS-51 Mode. Type / Length 0 Type / Length 1 Data 0 Data 1 … 30 ASIX ELECTRONICS CORPORATION ...
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... Issue the TXP command to the AX88796. This can be accomplished by writing 26H to the Command Register. 7. Read data current receive buffer by Remote DMA read operation. 8. Compare the received data with original transmit data and check equal. 9. Repeat step 5 to step 8 for more packets test. 3-in-1 Local Bus Fast Ethernet Controller 31 ASIX ELECTRONICS CORPORATION ...
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... Remote Byte Count 1 ( RBCR1 ) Receive Configuration Register ( RCR ) Transmit Configuration Register ( TCR ) Data Configuration Register ( DCR ) Interrupt Mask Register ( IMR ) Data Port IFGS1 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) GPOC Standard Printer Port (SPP) Reserved Reserved 32 WRITE ASIX ELECTRONICS CORPORATION ...
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... MAR4 ) Multicast Address Register 5 ( MAR5 ) Multicast Address Register 6 ( MAR6 ) Multicast Address Register 7 ( MAR7 ) Data Port Inter-frame Gap Segment 1 IFGS1 Inter-frame Gap Segment 2 IFGS2 MII/EEPROM Access Test Register Inter-frame Gap (IFG) GPOC Standard Printer Port (SPP) Reserved Reserved 33 WRITE ASIX ELECTRONICS CORPORATION ...
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... Packet Transmitted Indicates packet transmitted with no error 0 PRX Packet Received Indicates packet received with no error. 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION PS0 0 page 0 1 page 1 0 Not allowed 1 Remote Read 0 Remote Write 1 Not allowed X Abort / Complete Remote DMA DESCRIPTION 34 ASIX ELECTRONICS CORPORATION ...
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... These encoded configuration bits set the type of loop-back that performed. LB1 LB0 Mode 0 0 Mode 1 0 Mode CRC Inhibit CRC 0 : CRC appended by transmitter CRC inhibited by transmitter. 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 0 Normal operation 1 Internal AX88796 loop-back 0 PHYcevisor loop-back 35 ASIX ELECTRONICS CORPORATION ...
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... Receive Status Register (RSR) Offset 0CH (Read) FIELD NAME 7 - Reserved 6 DIS Receiver Disabled 5 PHY Multicast Address Received. 4 MPA Missed Packet 3 FO FIFO Overrun 2 FAE Frame alignment error CRC error. 0 PRX Packet Received Intact 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 36 ASIX ELECTRONICS CORPORATION ...
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... Test pin Enable, default value is logic 0 (User always keep the default value unchanged) 2:0 IFG Select Test Pins Output, default value is logic 0 (User always keep the default value unchanged) 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 37 ASIX ELECTRONICS CORPORATION ...
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... X 3:1 - Reserved 0 /GPO0 Default “0”. The register reflects to GPO[0] pin with inverted value. 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION GPI0 Media Selected 0 Internal PHY 1 Internal PHY 0 External MII PHY 1 Internal PHY X Depend on MPSET bit 38 ASIX ELECTRONICS CORPORATION ...
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... STRB Setting a low-high-low pulse on this register is used to strobe the print data into the printer. /STRB pin reflects the inverted value of this signal. 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION DESCRIPTION DESCRIPTION 39 ASIX ELECTRONICS CORPORATION ...
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... Device Specific 1 29 MR29 Device Specific 2 30 MR30 Device Specific 3 31 MR31 Quick Status Register Tab - 14 The Embedded PHY Registers 3-in-1 Local Bus Fast Ethernet Controller DESCRIPTION 40 ASIX ELECTRONICS CORPORATION DEFAULT(Hex Code) 3000h 7849h 0180h BB10h 01E1h 0000 0000 0000 - 0000 0000 0000 ...
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... This bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. The default state This bit is ORed with the F_DUP pin. Collision Test. When this bit is set the PHY will assert the MCOL signal in response to MTX_EN. Reserved. All bits will read 0. 41 ASIX ELECTRONICS CORPORATION ...
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... Jabber Detect. This bit will whenever a jabber condition is detected. It will remain set until it is read, and the jabber condition no longer exists. Extended Capability. This bit indicates that the PHY supports the extended register set (MR2 and beyond). It will always read ASIX ELECTRONICS CORPORATION ...
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... These bits are similar to the bits defined for the MR4 register (see Table 16). Selector Field. This field contains the type of message sent by the link partner. For IEEE 802.3 compliant link partners, this field should read 00001. 43 ASIX ELECTRONICS CORPORATION ...
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... Next Page Able. This bit is set to 1, indicating that this device supports the NEXT_PAGE function. Page Received. When this bit is set indicates that a NEXT_PAGE has been received. Link Partner Autonegotiation Capable. When this bit is set indicates that the link partner is autonegotiation capable. 44 ASIX ELECTRONICS CORPORATION ...
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... PCS macro. When this bit is low, only the collision pin is disabled in loopback. Scan Test Mode. Force Loopback. Force a loopback without forcing idle on the transmit side or disabling the collision pin. Speedup Counters. Reduce link monitor counter from 620 us. (Same as FASTTEST = 1.) 45 ASIX ELECTRONICS CORPORATION ...
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... Transmit Count Ack (FLP Xmit). Transmit Data Bit (FLP Xmit). Transmit Clock Bit (FLP Xmit). Transmit ability (FLP Xmit). Transmit Remaining Acknowledge (FLP Xmit). Idle (FLP Xmit). DESCRIPTION The data written into this user-defined register appears on the REG20_OUT[15:0] bus. 46 ASIX ELECTRONICS CORPORATION ...
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... Force Jam. This bit will latch high until read. This bit is only valid in 100Mbits/s mode. Link Up 100. This bit, when set indicates a 100Mbits/s transceiver is up and operational. Link Up 10. This bit, when set indicates a 10Mbits/s transceiver is up and operational. 47 ASIX ELECTRONICS CORPORATION ...
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... Setting this bit to 1 enables far-end fault detection, and logic 0 will disable the function. Default state is 0. Fiber-Optic Mode. When this bit the PHY is in fiber-optic mode. This bit is ORed with FX_MODE. 48 ASIX ELECTRONICS CORPORATION ...
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... When the PHY is in 100Mbits/s mode, this bit will be ignored. No Link Pulse Mode. Setting this bit will allow 10Mbits/s operation with link pulses disabled. If the PHY is configured for 100Mbits/s operation, setting this bit will not affect operation. 49 ASIX ELECTRONICS CORPORATION ...
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... Complete acknowledges. 101: FLP link good check. 110: Next page wait. 111: FLP link good. Highest Autonegotiation State. These 3 bits report the state of the highest autonegotiation state reached since the last register read, as defined above for bit [31.5:3]. 50 ASIX ELECTRONICS CORPORATION ...
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... SD[15:8] SD[7:0] High-Z High-Z Not Valid Even-Byte Not Valid Odd-Byte Odd-Byte Even-Byte SD[15:8] SD[7: Even-Byte X Odd-Byte Odd-Byte Even-Byte SD[15:8] SD[7:0] High-Z High-Z Not Valid Even-Byte Odd-Byte Not Valid Odd-Byte Even-Byte SD[15:8] SD[7: Even-Byte Odd-Byte X Odd-Byte Even-Byte ASIX ELECTRONICS CORPORATION ...
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... SA0 /IORD /IOWR SD[15:8] SD[7:0] High-Z High-Z Not Valid Odd-Byte Even-Byte Not Valid Even-Byte Odd-Byte SD[15:8] SD[7: Odd-Byte Even-Byte X Even-Byte Odd-Byte SD[15:8] SD[7:0] High-Z High-Z High-Z High-Z Not Valid Even-Byte Not Valid Odd-Byte SD[15:8] SD[7: Even-Byte X Odd-Byte ASIX ELECTRONICS CORPORATION ...
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... Tab - 16 MII Management Frames- field Description 3-in-1 Local Bus Fast Ethernet Controller (Internal PHY) MDC MDIO-OUT MDIO- (MUX (PHY_ID==10h) then S=1 else S=0 PHYAD REGAD TA DATA AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD AAAAA RRRRR 10 DDDDDDDDDDDDDDDD Descriptions 53 ASIX ELECTRONICS CORPORATION Pin67 MDC Pin66 MDIO IDLE Z Z ...
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... SYM Min Tpy Vdd +3.14 +3.30 SYM Min Tpy Vil - Vih 1.9 Vol - Voh Vdd-0.4 Iil -1 Iol -1 SYM Min Tpy SPt3v 94 54 ASIX ELECTRONICS CORPORATION Max Units °C +85 °C +150 +4.6 V 5.5* V Vdd+0.5 V °C +220 Max Units °C +75 +3.46 V Max Units 0 0 ...
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... If the auto negotiation time is not long enough, uncertain numbers of chip may not work properly. Countermeasure: 3-in-1 Local Bus Fast Ethernet Controller Thigh Tf Tlow Tcyc Min Min 100 55 Typ. Max Units Typ. Max Units - - LClk ASIX ELECTRONICS CORPORATION ...
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... Set the PHY register MR0 with 0x800h (1000,0000,0000) -- bit 11 of MR0 to '1' (Power down Mode). 2. Wait for 2.5 sec 3. Set the PHY register MR0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of MR0 to '1' (auto negotiation enable and restart auto negotiation) 3-in-1 Local Bus Fast Ethernet Controller 56 ASIX ELECTRONICS CORPORATION ...
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... Note: Tio(DS) is for data port only (Register 10 and 11) 3-in-1 Local Bus Fast Ethernet Controller Th(AEN) Tsu(A) Th(A) Tv(CS16-A) Ten(RD) Tdis(RDY) Tdis(RD) DATA Valid Tsu(WR) DATA Input Establish Min 0 160 57 Tio(DS) Tdis(CS16-A) Th(WR) Typ. Max Units - - ASIX ELECTRONICS CORPORATION ...
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... I/O CYCLE WIDTH TIME Note: Tio(DS) is for data port only (Register 10 and 11) 3-in-1 Local Bus Fast Ethernet Controller Tsu(A) Th(A) Tdis(RDY) Ten(RD) Tdis(RD) DATA Valid Tsu(WR) DATA Input Establish Min 0 160 58 ASIX ELECTRONICS CORPORATION Tio(DS) Th(WR) Typ. Max Units - - ...
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... OR /LDS WIDTH TIME Note: Tio(DS) is for data port only (Register 10 and 11) 3-in-1 Local Bus Fast Ethernet Controller Tsu(A) Th(A) Tw(DS) Ten(DS) Tdis(DTACK) Tdis(DS) DATA Valid Tsu(DS) DATA Input Establish Min 0 160 50 59 ASIX ELECTRONICS CORPORATION Tio(DS) Tdis(WR-DS) Th(DS) Typ. Max Units - - ...
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... I/O CYCLE WIDTH TIME Note: Tio(DS) is for data port only (Register 10 and 11) 3-in-1 Local Bus Fast Ethernet Controller Th(PSEN) Tsu(A) Th(A) Ten(RD) Tw(RW) Tdis(RDY) Tdis(RD) DATA Valid Tsu(WR) DATA Input Establish Min 0 160 60 ASIX ELECTRONICS CORPORATION Tio(DS) Th(WR) Typ. Max Units - - ...
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... Ttclk Ttch Ttcl Ttv Trclk Trch Trcl Trs Trs1 Min - - 14 140 14 140 - 140 14 140 Tth Trh Typ. Max Units 400 - 260 260 400 - 260 260 ASIX ELECTRONICS CORPORATION ...
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... AX88796 L 8.0 Package Information pin 1 b θ SYMBOL θ 3-in-1 Local Bus Fast Ethernet Controller MILIMETER MIN. NOM 0.05 0.1 1.35 1.40 0.17 0.22 13.90 14.00 19.90 20.00 0.5 15.60 16.00 21.00 22.00 0.45 0.60 1.00 0° 62 ASIX ELECTRONICS CORPORATION MAX 0.15 1.45 1.6 0.27 14.10 20.10 16.40 23.00 0.75 7° ...
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... Note : The capacitors (33pf) may be various depend on the specification of crystal. While designing, please refer to the suggest circuit provided by crystal supplier. A.2 Using Oscillator 25MHz AX88796 XTALIN 3.3V Power OSC 25MHz 3-in-1 Local Bus Fast Ethernet Controller CLKO25M 25MHz XTALOUT 33pf CLKO 25M 25MHz XTALOUT NC 63 ASIX ELECTRONICS CORPORATION ...
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... Full traffic with 10Mbps at full-duplex mode, no LED drive 15 Full traffic with 100Mbps at half-duplex mode, no LED drive 16 Full traffic with 100Mbps at full-duplex mode, no LED drive 3-in-1 Local Bus Fast Ethernet Controller Test Conditions 64 ASIX ELECTRONICS CORPORATION Typical Value Units – ...
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... PTX bit asserted rather than TXE asserted. Solution: Packet collided 16 times and aborted is normal way, even that is rare happen in live network, in very heavy traffic. While the upper protocol layer will handle the situation and cover the packet loss. 3-in-1 Local Bus Fast Ethernet Controller 65 ASIX ELECTRONICS CORPORATION ...
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... DIP 100mil & SMD 1206 66 SD[0..7]] SA[0..9] SA[0..9] SD[0..15] SD[0..15] BHE# BHE# IORD# IORD# IOWR# IOWR# AEN AEN RESET RESET IRQ IRQ RDY RDY IOIS16# IOIS16# 3.3V 3.3V GND GND SA[0..9] SD[8..15] ASIX ELECTRONIC CORPORATION Title ISA BUS Size Document Number A4 796NS3A.SCH Date: Thursday , April 19, 2001 Sheet ASIX ELECTRONICS CORPORATION Rev 2 ...
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... ON OFF + ON ON 0.1u 4.7uF/16V ON ON SMD 1206 ASIX ELECTRONICS CORPORATION Title AX88796 Size Document Number A3 796NS3A1.SCH Date: Thursday, April 19, 2001 ASIX ELECTRONICS CORPORATION RXER RXER RXDV RXDV COL COL CRS CRS RXCK RXCK RXD0 RXD0 RXD1 RXD1 RXD2 RXD2 RXD3 RXD3 TXCK ...
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... R13 4.7K COLLED R15 R33 4.7K 9.31K SPDLED R17 1% 4.7K GND PWRLED R19 4.7K LED4 R14 D5 LED 330 LED5 R10 D4 LED 330 R16 LED6 D6 LED 330 ASIX ELECTRONICS CORPORATION Title DP83851C Size Document Number A4 796NS3A2.SCH Date: Thursday , April 19, 2001 Sheet ASIX ELECTRONICS CORPORATION Rev 2.0 ...
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... R40 RJ45N 75 GND_CH TIP 4 RING RJ11 TIP 4 RING RJ11-S ASIX ELECTRONIC CO. Title RJ45 & RJ11 Size Document Number A4 796NS3A3.SCH Date: Wednesday, May 22, 2002 Sheet ASIX ELECTRONICS CORPORATION Rev 2 ...
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... AX88796 L 3-in-1 Local Bus Fast Ethernet Controller THIS PAGE LEFT BLANK 70 ASIX ELECTRONICS CORPORATION ...
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... Modify RDY timing diagram in ISA and 186 mode 3 Remove BOS bit in DCR register 4 Include LED current sink value Schematic change for hi-voltage Cap, change from 0.01u to 1000PF 1. Add Tio (DS) timing information to all modes 4F, NO.8, HSIN ANN RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C. support@asix.com.tw http://www.asix.com.tw 71 ASIX ELECTRONICS CORPORATION ...