W3100A ETC-unknow, W3100A Datasheet
W3100A
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W3100A Summary of contents
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... Description The i2Chip W3100A is an LSI of hardware protocol stack that provides an easy, low-cost solution Description for high-speed Internet connectivity for digital devices Features by allowing simple installation of TCP/IP stack in the Block Diagram hardware. The W3100A offers system designers a quick, easy way to add Ethernet networking functionality to any product ...
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Table of Contents ; ; ~p•Œ›GšGyhwpkGOyŒœšˆ‰“ŒGh——“Šˆ›–•Tš—ŒŠŠGp•›Œ““ŒŠ›œˆ“Gw™–—Œ™› GkŒŒ“–—Œ™PH ...
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... W3100A 64-LQFP ...
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... Interface mode. I ADDRESS PINS DATA PINS O INTERRUPT: Indicates that the W3100A requires MCU attention after reception or transmission. The interrupt is cleared by writing to the ISR (Interrupt Status Register). All interrupts are maskable by writing IMG (Interrupt Mask Register). This signal is active low. I CHIP SELECT: This signal is active low. ...
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... MHz clock rate on the least significant bits of the nibble-wide MII data buses, pins TXD[0] and RXD[0], respectively. This mode is intended for use with the W3100A connected to a PHY using a 10 Mb/s serial interface. There is an internal pull-up resister for this pin. If this pin is left floated externally, then the device will be configured to normal mode ...
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... Test mode Clocked mode, External clocked mode and Non-clocked mode are used to connect MCU and W3100A when MCU Bus I use. Choose an appropriate mode and use it by analyzing the MCU bus timing. Refer to timing diagram for each mode for more detail. ...
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... Table5. W3100A Registers Map Address Register 0x00 C0_CR S/W Reset 0x01 C1_CR Memory Test 0x02 C2_CR 0x03 C3_CR 0x04 C0_ISR 0x05 C1_ISR 0x06 C2_ISR 0x07 C3_ISR 0x08 IR 0x09 IMR IM_C3R 0x0A – 0x0B Reserved 0x0C IDM_OR IND_EN 0x0D IDM_AR0 Indirect bus I/F mode Address0 Register ...
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C2_RW_PR Channel 2 Rx Write Pointer Register 0x2C – 0x2F C2_RR_PR Channel 2 Rx Read Pointer Register 0x30 – 0x33 C2_TA_PR Channel 2 Tx ACK Pointer Register 0x34 – 0x37 C3_RW_PR Channel 3 Rx Write Pointer Register ...
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RCR 0x95 RMSR Rx data Memory Size Register 0x96 TMSR Tx data Memory Size Register 0x97 – 0x9F Reserved 0xA0 C0_SSR Channel 0 Socket Status Register 0xA1 C0_SOPR Broadcast/ERR 0xA2 – 0xA7 Reserved 0xA8 – 0xAB C0_DIR Channel 0 ...
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Reserved 0xD0 C2_SSR Channel 2 Socket Status Register 0xD1 C2_SOPR Broadcast 0xD2 – 0xD7 Reserved 0xD8 – 0xDB C2_DIR Channel 2 Destination IP Address Register 0xDC – C2_DPR Channel 2 Destination Port Register 0xDD 0xDE – 0xDF ...
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Register Definitions. Register sets are categorized into (i) control registers related to command, status and interrupt, (ii) system registers for gateway address, subnet mask, source IP, source HA (Hardware Address) and timeout value, (iii) pointer registers for managing to send, ...
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... Set memory test bit to ‘1’ to become toggled as ‘0’, ‘1’ and W3100A acts in memory test mode when in ‘1’. Memory test bit needs to become set at ‘0’ in order for W3100A to execute normal data transmission and reception. ...
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D1 Sock_Init Sets corresponding protocol at Cx_SOPR and opens corresponding channel socket D2 Connect Command for corresponding channel socket to act in client mode to make a connection to the server D3 Listen Command to stand by for connection when ...
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C1_ISR, C2_ISR, C3_ISR (Channel Interrupt Status Register) [R, 0x05, 0x06, 0x07] This register notifies the outcome of the command of each Channel 1, 2 and 3. This register becomes cleared as 0x00 by read operation. Established notifies ...
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C3R C2R C1R Bit Symbol D0 C0 Occurrence of Channel 0 Socket Interrupt D1 C1 Occurrence of Channel 1 Socket Interrupt D2 C2 Occurrence of Channel 2 Socket Interrupt D3 C3 Occurrence of Channel 3 Socket Interrupt D4 ...
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AUTO_INC (auto-increment) bit automatically increases the address during an access to indirect data register IND_EN Bit Symbol D7 IND_EN Indirect bus I/F mode Enable. D6 Reserved D5 Reserved D4 Reserved D3 Reserved D2 Reserved D1 L/B Little-endian/Big-endian ordering ...
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SHAR (Source Hardware Address Register) [R/W, 0x88 – 0x8D] This register sets up the used in the system, which is required to be set up before executing Sys_Init command. SIPR (Source IP Address Register) [R/W, 0x8E – ...
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TMSR (Tx data Memory Size Register) [R/W, 0x96] This register allocates 8KB of transmitted memory for each channel. CH3 Memory size 0 0 1KB 0 1 2KB 1 0 4KB 1 1 8KB 2 bits ...
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... Included in each channel, this register displays the current working pointer of the data to be transmitted when transmitting data. The register, used internally in W3100A, displays the pointer to start transmission when transmission is made by send command. oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUP ...
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... Socket initializing Applicable channel is initialized in UDP mode Applicable channel is initialized in IP layer RAW mode Standing by for reply after transmitting ARP request packet to the destination for UDP transmission Data transmission in progress in UDP or RAW mode W3100A initialized in MAC layer RAW mode G after YW ...
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SOPR (Socket Option and Protocol Register) [R/ 0xA1 B9 D1 E9] This register sets up socket option or protocol of the corresponding channel NDAck Broadcast/ NDTimeout/ ERR ...
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... C3 : 0xF0 – 0xF3] This register sets the Destination IP Address of each channel to be used in setting the TCP connection. In active mode, IP address needs to be set before executing the Connect command. In passive mode, W3100A sets up the connection and then updates as peer IP internally. DPR (Destination Port Register) [R/ 0xAC – 0xAD 0xC4 – 0xC5 0xDC – ...
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... Not used WŸ[WWWG Tx data buffer WŸ]WWWG Rx data buffer WŸ_WWWG W3100A internal register and memory are comprised of 512 byte Control Registers and 16KB data buffer as displayed in the diagram above. - 0x0000 ~ 0x00FF: Space for Control Registers - 0x0100 ~ 0x01FF: Space for Shadow Registers ...
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... In order to verify the active status of Tx data buffer and Rx data buffer, MCU can execute both write and read by setting the memory test mode (setting up of C1_CR memory test bit). In memory test mode, however, W3100A cannot execute proper transmission and reception of data. Memory test mode must be terminated for normal operation of W3100A. ...
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... Description of Functions 1. Initialization of W3100A In order to use W3100A, the basic registers that are required to run W3100A need to be set up. The basic registers include GAR (Gateway Address Register), SMR (Subnet Mask Register), SHAR (Source Hardware Address Register), and SIPR (Source IP Address Register). GAR, SMR and SIPR are the network information on which W3100A is operated, and the registers need to be set according to the operating environment ...
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... When no reply is received within the designated timeout duration, timeout occurs and it changes to CLOSED state. d. SYNSENT state: In this state, W3100A transmits SYN packet and stands by to receive SYN,ACK packet from the peer. In case appropriate SYN,ACK packet is received, W3100A transmits ACK packet and completes the connection set-up to become changed to ESTABLISHED state ...
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CLOSED cmd : sys_init, close Timeout recv : RST ESTABLISHED a. CLOSED state: channel is initialized by executing sys_init or close command b. INIT state: sets the port number (source port register used in the channel ...
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... FIN and creates closed interrupt at MCU. By processing the interrupt, MCU executes the close command to W3100A and completes the connection close. But, if data to be sent still are left, that is TW_PR value is not equal to TA_PR value, you should not issue the close command but wait until timeout occurs or ignore close procedure and make progress next step like sock_init command ...
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... TCP Transmission Memory Size Set-up W3100A transmission memory is comprised of 8KB in total, and the size can be assigned for each channel through TMSR register. An example of TMSR and each memory size is illustrated in the diagram below. When the memory size from channel 0 exceeds 8KB, all ensuing memory is ignored. ...
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... Above diagram illustrates the change in Cx_TW_PR and Cx_TA_PR when actual data transmission is made after 2KB of transmission memory is set at CH0. TCP Reception Memory Size Set-up Receiving memory of W3100A has the same structure of the transmission memory and operated in same method. The memory is comprised of 8KB in total, and the size can be assigned for each channel through RMSR (Rx data Memory Size register) ...
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... Cx_RR_PR <= Cx_RR_PR + LEN TCP data reception by W3100A is illustrated in the above diagram. In W3100A, when data is received from the peer, the data is recorded as reception memory from Cx_RW_PR (Rx Write Pointer Register of Chnnel x), Cx_RW_PR is increased according to the size of the received data when the reception is complete, and then MCU is interrupted to report a data reception ...
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... UDP is a connectionless protocol. No connection set-up or termination process is needed, thereby creating lesser load. UDP Initialization Process In order to use UDP of W3100A, the Cx_SOPR (Socket Option/Protocol register of Channel x) protocol field of the corresponding channel needs to be set as SOCK_DGRAM(0x02) before socket initialization. Unlike TCP, data transmission and reception is possible at UDP without any connection set-up process. ...
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... Above diagram illustrates the change in Cx_TW_PR and Cx_TA_PR when actual data transmission is made after 2KB of transmission memory is set at CH0. UDP Data Reception W3100A’s UDP reception is similar to TCP reception. The difference is that the header information for UDP processing is included in the received data in addition to the data. The header is structured as below. TLEN ...
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... When Cx_RW_PR is When Cx_RW_PR is increased by receiving increased by receiving data from the peer at data from the peer at W3100A W3100A G 0x0800 0x0800 Cx_RW_PR is Cx_RW_PR increased to 0x00123580 (W3100A) 0x0580 Rx 0x0580 Data head 0x0400 Cx_RR_PR is increased to 0x0200 0x00123400 (MCU) Cx_RR_PR 0x0000 0x0000 When MCU completes ...
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... UDP as provided by W3100A. IPL_RAW Mode Initialization Process In order to use W3100A’s IPL_RAW Mode, the protocol value of the IP Layer to be used (e.g., 0x01 in case of ICMP) needs to be set as Cx_IPR (IP Protocol Register of Channel x), and the Cx_SOPR (Socket Option/Protocol register of Channel x) protocol field of the corresponding channel needs to be set as SOCK_IPL_RAW(0x03) before socket initialization (sock_init command) ...
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... If MAC Layer RAW Mode is used, W3100A uses Channel 0 only and other channels are ignored. oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUP ...
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... C0_TW_PR is equal increased to 0x00000200 (MCU) 0x0200 0x0200 Tx C0_TR_PR Data 0x0000 0x0000 When MCU records the transmission data for transmission and C0_TW_PR is increased G C0_TW_PR C0_TR_PR is increased to 0x00000200 (W3100A) Z^ ...
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... Channel 0. Above diagram illustrates the processing of 2 data after C0_WR_PR and C0_RR_PR are equally initialized as 0x00000200. MACL_RAW Mode Data Reception In W3100A’s MACL_RAW Mode, the reception of the set packets are made according to the receive options as set at C0_SOPR UDP, header information is included in the received data in addition to the data, and the header is structure as below. ...
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TLEN STT shown in the above diagram, the header information IPL_RAW mode contains (1) TLEN identical to UDP TLEN displaying the total length of data and header length, and (2) 1 Byte STT displaying the status ...
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... However, some systems require faster access (access time of less than 100ns) to the W3100A, in which case either the External clocked mode or the Non-clocked mode should be selected. Non-clocked mode should be used in a situation where /CS granted to the W3100A drops to low as in the access timing diagram on page 54 and /RD or /WR goes low after 10ns. Otherwise, External clocked mode should be used ...
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... MCU bus I/F is activated by the External clock. In Non-clocked mode, the internal functions of W3100A are executed by the clock granted to the clock pin, and the MCU bus I/F is activated by /CS, /RD, /WR of MCU. As shown in the timing diagram, and unlike Clocked mode and External clocked mode, a timing condition exists between /CS, /RD, and /WR. ...
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... IDM_AR0,1. Later, when IDM_DR is read, the value of the register to be accessed is read. In order to write the internal register value of W3100A, the address of the internal register to be accessed needs to be written at IDM_AR0,1. Later, the value can be written at IDM_DR. The L/B bit of IDM_OR that sets up the order when accessing IDM_AR0,1 functions as below: If L/B bit of IDM_OPT register = ‘ ...
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... SDA Device address set-up A simple block diagram as shown above illustrates the connection between MCU and W3100A using I As illustrated above recommended to set the device address for I of 4.7 SCL and SDA lines externally, and then ground the remaining address A[7:0]. k for oˆ ...
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... In order to synchronize MCU and W3100A I/F creates the condition for START before transmitting and receiving data, and the condition for STOP is created after the completion of data transmission and reception. When SDA line becomes low while SCL line is high, it becomes the signal for the condition for START. When SDA line becomes high while SCL line is high, it becomes the signal for the condition for STOP ...
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START, DEVICE ADDRESS, 2 Byte address of the actual register to be accessed, and the actual data before sending STOP. In ...
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Sequential byte write sequentially sends START, DEVICE ADDRESS, 2 Byte address of the actual register to be accessed, and data to be written before sending STOP result, MCU can designate the address of the data to be written ...
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SEQUENTIAL BYTE READ DEVICE R T ADDRESS T E SDA LINE DEVICE R ...
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... This mode is the I/F for 10Mbps Physical Layer Devices, and is composed of 1-bit TXD and RXD. TX_CLK and RX_CLK use a 10MHz cycle. When linking the W3100A with the Physical Layer Device in this mode, RXD and TXD of the Physical Layer Device must be connected to RXD[0] and TXD[0] of the W3100A. ...
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... This mode is the I/F for 10/100Mbps Physical Layer Devices, and is composed of 4-bit TXD[0:3] and RXD[0:3]. TX_CLK and RX_CLK use a 2.5MHz cycle at 10Mbps and 25MHz at 100Mbps. When linking the W3100A with the Physical Layer Device in this mode, RXD[0:3] and TXD[0:3] of the Physical Layer Device must be connected to RXD[0:3] and TXD[0:3] of the W3100A. ...
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Timing Diagrams 1. Clocked mode(CLOCK = 25MHz) TIMING WAVEFORM OF Register/Memory READ CYCLEG G h‹‹™ŒššG jzG ykG kˆ›ˆG–œ›G oŽTG TIMING WAVEFORM OF Register/Memory WRITE CYCLE G G h‹‹™Œšš jzG ~ ...
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AC Characteristics Direct Mode Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Read Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip ...
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External clocked mode(EXT_CLK = 50MHz) TIMING WAVEFORM OF Register/Memory READ CYCLEG G h‹‹™ŒššG jzG ykG kˆ›ˆG–œ›G oŽTG TIMING WAVEFORM OF Register/Memory WRITE CYCLE G G h‹‹™Œšš jzG ~ ...
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AC Characteristics Direct Mode Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Read Chip disable to high-Z output Output disable to high-Z output Output hold from address change Chip ...
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Non-clocked mode(CLOCK = 25MHz) TIMING WAVEFORM OF Register/Memory READ CYCLEG G h‹‹™ŒššG jzG ykG kˆ›ˆG–œ›G oŽTG TIMING WAVEFORM OF Register/Memory WRITE CYCLE / / / / / / / / h‹‹™Œšš ...
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AC Characteristics Direct Mode Chip select to output Chip select low to Read low Output enable to valid output Chip select to low-Z output Output enable to low-Z output Read Read high to Chip select high Chip disable to high-Z ...
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Indirect Mode Chip select to output Chip select low to Read low Output enable to valid output Chip select to low-Z output Output enable to low-Z output Read Read high to Chip select high Chip disable to high-Z output Output ...
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I C mode(CLOCK = 25MHz BUS START/STOP BITS TIMINGG zjsG › G zhz › zho zkhG z{hy BUS DATA TIMING zjsG › zkhG zkhG oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUP G › › ...
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AC Characteristics START condition setup time START / START condition hold time STOP STOP condition setup time BITS TIMING STOP condition hold time Clock Frequency, SCL SCL high time SCL low time BUS SDA, SCL rise time DATA SDA, SCL ...
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Media Independent Interface (MII) MII Tx TIMING G {†jsr {†lu {k AC Characteristics Parameter Description Tco TX_CLK to TXD, TX_EN Tdcs TXD, TX_EN setup time to TX_CLK Tco TX_CLK to TXD, TX_EN Tdcs TXD, TX_EN setup time to TX_CLK ...
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G MII Rx TIMING y†jsr y†lu y Characteristics Parameter Description Tdcs Valid Data to RX_CLK (setup) Tcdh RX_CLK to Valid Data (hold) Tdcs Valid Data to RX_CLK (setup) Tcdh RX_CLK to Valid Data (hold) oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUP ˆ“‹G‹ˆ›ˆ {‹Šš {Š‹ ...
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... Package Description G Figure 1: W3100A LQFP Package Specifications G oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUP ...
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Appendix A. Electrical Specifications ABSOLUTE MAXIMUM RATINGS Symbol Parameter V DC supply voltage input voltage input current IN T Storage temperature STG *COMMENT: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent ...
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POWER DISSIPATION Symbol Minimum P Typical 10BASE Maximum Minimum P Typical 100BASE Maximum G oˆ™‹ž™Œ‹Gp•›Œ™•Œ›Gj–••ŒŠ›› G~¡ˆ™‹GO~p•Œ›SGp•ŠUP Condition G Power Consumption Unit ...