VT82C596B ETC-unknow, VT82C596B Datasheet
VT82C596B
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VT82C596B Summary of contents
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... Updated feature bullets, overview, and pin descriptions Replaced IDE function 1 with registers from 686B to reflect UltraDMA-66 Added / changed PMU function 3 registers Rx42[7-6, 4], Rx58-5B, PMU I/O Offset 0[8], 2C[2], 30[10-0], 34[10-0], 38[6, 4-3], 40 (removed) Changed Function 0 Rx42[2-0], 43[5-4], 50 default, 55[3-0], 57[3-0], 58[3-0], 88[5], Function 1 RxD, 42-43, 45[3-2], 54[4-3], 70, 74-75, 78, 7C-7D, Function 2 Rx41[7-3], Function 3 Rx4C-4F default value -i- VT82C596B Initials Revision History ...
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... Processor Bus States ............................................................................................................................................................................. 78 System Suspend States and Power Plane Control ................................................................................................................................. 79 General Purpose I/O Ports..................................................................................................................................................................... 79 Power Management Events ................................................................................................................................................................... 80 System and Processor Resume Events .................................................................................................................................................. 80 Legacy Power Management Timers ...................................................................................................................................................... 81 System Primary and Secondary Events ................................................................................................................................................. 81 Peripheral Events .................................................................................................................................................................................. 81 ELECTRICAL SPECIFICATIONS............................................................................................................................................... 82 Revision 0.3 June 17, 1999 T C ABLE OF ONTENTS -ii- VT82C596B Table of Contents ...
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... BSOLUTE AXIMUM ATINGS DC C ................................................................................................................................................................ 82 HARACTERISTICS ...................................................................................................................................................... 83 IMING PECIFICATIONS PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 90 Revision 0.3 June 17, 1999 ................................................................................................................................................. 82 -iii- VT82C596B Table of Contents ...
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... FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C596B ................................................................................. 3 FIGURE 2. VT82C596B BALL DIAGRAM (TOP VIEW)........................................................................................................... 4 FIGURE 3. VT82C596B PIN LIST (NUMERICAL ORDER)...................................................................................................... 5 FIGURE 4. VT82C596B PIN LIST (ALPHABETICAL ORDER)............................................................................................... 6 FIGURE 5. STRAP OPTION CIRCUIT....................................................................................................................................... 40 FIGURE 6. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 78 FIGURE 8. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 85 FIGURE 9 ...
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... Integrated physical layer transceivers with over-current detection status on USB inputs Legacy keyboard and PS/2 mouse support Advanced Programmable Interrupt Controller (APIC) Integrated on-chip Control pins provided for support of optional external APIC Used to extend system interrupt capability PC98 compliant Revision 0.3 June 17, 1999 VT82C596B PIPC P NTEGRATED ERIPHERAL PCI- OMPLIANT TO P ...
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... PCI interrupts steerable to any interrupt channel Dual interrupt and DMA signal steering for on-board plug and play devices Microsoft Windows 95 Built-in NAND-tree pin scan test capability 0.5u, 3.3V, low power CMOS process Single chip 324 pin BGA Revision 0.3 June 17, 1999 TM and plug and play BIOS compliant -2- VT82C596B Features ...
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... IDE controller is SFF-8038i v1.0 and Microsoft Windows- compliant. b) Universal Serial Bus controller that is USB v1.1 and Universal HCI v1.1 compliant. The VT82C596B includes the root hub with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support ...
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... Note: Some of the pins above have alternate functions and alternate names. The table above contains only one name, but the pin lists and pin descriptions contain all names. Revision 0.3 June 17, 1999 P INOUTS Figure 2. VT82C596B Ball Diagram (Top View ...
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... Figure 3. VT82C596B Pin List (Numerical Order) Pin Pin Name Pin Pin Name A01 O PCIRST# D06 IO AD14 A02 IO AD27 D07 IO AD10 A03 I IDSEL D08 IO AD6 A04 IO AD19 D09 IO AD2 A05 IO FRAME# D10 P GND A06 I SERR# D11 I PCLK A07 IO AD13 ...
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... Figure 4. VT82C596B Pin List (Alphabetical Order) Pin Pin Name Pin P01 IO A20GATE / MSCK K19 I M20 OD A20M# A05 IO FRAME# B10 IO AD00 D10 P GND A10 IO AD01 E07 P GND D09 IO AD02 E13 P GND C09 IO AD03 J09 P GND B09 IO AD04 J10 P GND ...
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... IO PCI Bus Clock Run. This signal indicates whether the PCI clock is or will be stopped (high) or running (low). The VT82C596B drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping ...
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... OD Initialization. The VT82C596B asserts INIT if it detects a shut-down special cycle on the PCI bus soft reset is initiated by the register OD Stop Clock. STPCLK# is asserted by the VT82C596B to the CPU in response to different Power-Management events. OD System Management Interrupt. SMI# is asserted by the VT82C596B to the CPU in response to different Power-Management events. ...
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... UltraDMA mode signals the termination of the burst. I Primary Device DMA Request. Primary channel DMA request I Secondary Device DMA Request. Secondary channel DMA request O Primary Device DMA Acknowledge. Primary channel DMA acknowledge O Secondary Device DMA Acknowledge. Secondary channel DMA acknowledge -9- VT82C596B Pinouts ...
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... Primary Disk Address. PDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. O Secondary Disk Address. SDA[2:0] are used to indicate which byte in either the ATA command block or control block is being accessed. IO Primary Disk Data IO Secondary Disk Data -10- VT82C596B Pinouts ...
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... ISA data bus. O ISA Bus Address Latch Enable. BALE is an active high signal asserted by the VT82C596B to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid IO ISA 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles ...
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... DMA Request. Used to request DMA services from the internal DMA controller. O Acknowledge. Used by the internal DMA controller to indicate that a request for DMA service has been granted. O Terminal Count. Asserted to DMA slaves as a terminal count indicator. O Speaker Drive. The output of internal timer/counter 2. -12- VT82C596B Pinouts ...
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... ROM Chip Select. Chip Select to the BIOS ROM. O Microcontroller Chip Select. Asserted during read or write accesses to I/O ports 62h or 66h. O Programmable Chip Selects. Asserted during I/O cycles to programmable read or write ISA address ranges. Devices selected by these pins are assumed the X- Bus (XDIR# and XOE# are enabled). -13- VT82C596B Pinouts ...
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... Keyboard Controller Chip Select. (Rx76[2]=0 external keyboard controller enabled) Chip select for external keyboard controller. General Purpose Output 26 disabled) General purpose output Rx5A[1]=1 (Internal keyboard controller enabled –strapped from XD1) Mouse Data. Mouse data (extended function not available on PIIX4) -14- VT82C596B (Rx76[2]=1 external keyboard controller Pinouts ...
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... External APIC Acknowledge. (Rx74[7]=1 & Rx74[1]=0) Asserted by the VT82C596B to indicate that it internal buffers have been flushed (in response to APICREQ#). This indicates to the external APIC that the VT82C596B’s internal buffers have been flushed and that for the APIC to send its interrupt. General Purpose Output 12. (Rx74[ ...
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... ACPI I/O Space (Function 3) is enabled I General Purpose Input 14. I General Purpose Input 15. I General Purpose Input 16. I General Purpose Input 17. I General Purpose Input 18. I General Purpose Input 19. I General Purpose Input 20. (Rx59[ See also Rx55[3:0] I General Purpose Input 21. (Rx59[ See also Rx58[3:0] -16- VT82C596B Pinouts ...
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... General Purpose Output 22. Rx75[ General Purpose Output 23. Rx75[ General Purpose Output 24. Rx76[ General Purpose Output 25. Rx76[ General Purpose Output 26. Rx76[ General Purpose Output 27. O General Purpose Output 28. O General Purpose Output 29. Rx74[ General Purpose Output 30. -17- VT82C596B Pinouts ...
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... Power Management I/O Signal Description I Power Button. Used by the Power Management subsystem to monitor an external system on/off button or switch. The VT82C596B performs a 200us debounce of this input if Rx40[5] is set to 1. This input is referenced to VCCSUS. I ACPI Sleep Button. General purpose input 13, but also functions as the ACPI sleep button if bit-9 of register 0 of ACPI I/O Space (Function 3) is enabled ...
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... VCCSUS. May optionally be programmed as a general purpose input (Rx74[6]=1). I Thermal Detect. If the VT82C596B is enabled to allow it, asserting this signal initiates hardware Clock Throttling mode. This causes STPCLK cycled at a preset programmable rate (see Function 3 configuration space Rx4C). May optionally be programmed as a general purpose input (Rx74[2]=1) ...
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... I/O Signal Description I Power Good. Connected to the PWRGOOD signal on the Power Supply. O PCI Reset. Active low reset signal for the PCI bus. The VT82C596B will assert this pin during power-up or from the control register. O Reset Drive. Reset signal to the ISA bus. O Bus Clock. ISA bus clock. ...
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... R EGISTERS Register Overview The following tables summarize the configuration and I/O registers of the VT82C596B. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’ ...
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... Default Acc D2 Write Request RW D4 Write Single Mask D6 Write Mode Default Acc D8 Clear Byte Pointer FF — Master Clear — Clear Mask — Read / Write Mask — RW -22- VT82C596B Default Acc Register Overview ...
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... RW 83 ISA Positive Decoding Control 3 00 — 84 ISA Positive Decoding Control 85-86 -reserved- 00 — 87 Test Test PLL Control 0300 RW 8A-FF -reserved- -23- VT82C596B Default Acc — x4† — Default ...
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... Offset IDE I/O Registers 0 Primary Channel Command 1 -reserved- 2 Primary Channel Status 3 -reserved- 4-7 Primary Channel PRD Table Addr 8 Secondary Channel Command 9 -reserved- A Secondary Channel Status B -reserved- C-F Secondary Channel PRD Table Addr -24- VT82C596B Default Acc A8A8A8A8 RW FF ...
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... Port 1 Status / Control 0C RO 13-12 Port 2 Status / Control — 00000301 RW 00 — — Default Acc — — 2000 RW 00 — -25- VT82C596B Default Acc 0000 RW 0000 WC 0000 RW 0000 RW 00000000 0080 WC 0080 WC Register Overview ...
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... Offset System Management Bus 93-90 SMBus I/O Base 94-D1 -reserved- D2 SMBus Control D3 SMBus Host Slave Command D4 SMBus Slave Address for Port 1 D5 SMBus Slave Address for Port 2 D6 SMBus Revision ID D7-FF -reserved- -26- VT82C596B Default Acc — 0000 RW 0000 RW 0000 0001 RW 00 ...
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... Primary Activity Detect Enable 3B-38 GP Timer Reload Enable 3C-3F -reserved- Offset General Purpose I/O Registers 40 General Purpose Control 41-43 -reserved- 45-44 External SMI Input Value 46-47 -reserved- 4B-48 GPI Port Input Value 4F-4C GPO Port Output Value 50-FF -reserved- -27- VT82C596B Default Acc 0000 WC 0000 RW 0000 RW 00 — 0000 0000 RW 00 — ...
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... Register Number Used to select a specific DWORD in the device’s configuration space 1-0 Fixed ........................................ always reads 0 Port CFF-CFC - Configuration Data .............................. RW Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers. Revision 0.3 June 17, 1999 -28- VT82C596B Configuration Space I/O ...
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... Enable Timer/Counter 2 Revision 0.3 June 17, 1999 Port 92h - System Control ................................................ RW 7-6 5 (duplication of that -29- VT82C596B Hard Disk Activity LED Status 0 Off .................................................... default 1-3 On Reserved ........................................always reads 0 Power-On Password Bytes Inaccessable ..default=0 Reserved ........................................always reads 0 A20 Address Line Enable 0 A20 disabled / forced 0 (real mode) ...... default ...
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... System Flag ................................................ default=0 This bit may be read back as status register bit-2 1 Mouse Interrupt Enable 0 Keyboard Interrupt Enable -30- VT82C596B 0 Keyboard Output Buffer Empty............. default 1 Keyboard Output Buffer Full 0 Input Buffer Empty................................ default 1 Input Buffer Full 0 Power-On Default .................................. default 1 ...
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... Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT82C596B are listed n the table below. Note: The VT82C596B Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Controller except that due to its integrated nature, many of the ...
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... Channel 3 DMA Page (M-3).........RW 0000 0000 1000 1111 Channel 4 DMA Page (S-0) ..........RW 0000 0000 1000 1011 Channel 5 DMA Page (S-1) ..........RW 0000 0000 1000 1001 Channel 6 DMA Page (S-2) ..........RW 0000 0000 1000 1010 Channel 7 DMA Page (S-3) .........RW -32- Register Descriptions - Legacy I/O Ports VT82C596B ...
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... Note that not all bits of the address are decoded. The Timer / Counters are compatible with the Intel 8254 Timer / Counter chip. Detailed descriptions of 8254 Timer / Counter operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications. -33- Register Descriptions - Legacy I/O Ports VT82C596B ...
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... Month Alarm 7F Century Field 80-FF Software-Defined Storage Registers (128 Bytes) (See also Function 0 Rx5B[3] and Rx77[2-1]) For reference, the Table 5. CMOS Register Summary -34- VT82C596B Binary Range BCD Range 00-3Bh 00-3Bh 00-3Bh 00-3Bh am 12hr: 01-1Ch pm 12hr: 81-8Ch 24hr: 00-17h am 12hr: 01-1Ch ...
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... Function 0 Registers - PCI to ISA Bridge All registers are located in the function 0 PCI configuration space of the VT82C596B. These registers are accessed through PCI configuration mechanism #1 via I/O address CF8/CFC. PCI Configuration Space Header Offset 1-0 - Vendor ID = 1106h ......................................... RO Offset 3-2 - Device ID = 0596h .......................................... RO Offset 5-4 - Command ....................................................... RW 15-8 Reserved ...
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... PCICLK/3.............................................. default 001 PCICLK/2 010 PCICLK/4 011 PCICLK/6 100 PCICLK/5 101 PCICLK/10 110 PCICLK/12 111 OSC Note: Procedure for ISA CLOCK switching: 1) Set bit Change value of bit 2-0; 3) Set bit -36- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... Write Delay Transaction Time-Out Timer Enable 0 Disable................................................... default 1 Enable 1 Read Delay Transaction Time-Out Timer Enable 0 Disable................................................... default 1 Enable 0 Software PCI Reset ......write 1 to generate PCI reset -37- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... Forward D8000-DBFFF Accesses to PCI ......def=0 5 Forward D4000-D7FFF Accesses to PCI .......def=0 4 Forward D0000-D3FFF Accesses to PCI .......def=0 3 Forward CC000-CFFFF Accesses to PCI .....def=0 2 Forward C8000-CBFFF Accesses to PCI ......def=0 1 Forward C4000-C7FFF Accesses to PCI .......def=0 0 Forward C0000-C3FFF Accesses to PCI .......def=0 -38- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... IRQ15 Offset 59 - PIRQ Pin Configuration (04h) ...................... RW 7-3 Reserved ........................................always reads 0 2 PIRQ2 / GPI21 Selection (Pin G3) 0 PIRQ2 1 GPI21 .................................................... default 1 PIRQ1 / KEYLOCK Selection (Pin J4) 0 PIRQ1 .................................................... default 1 KEYLOCK 0 PIRQ0 / GPI20 Selection (Pin H5) 0 PIRQ0 .................................................... default 1 GPI20 -39- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... External APIC on XD Bus..................... default 1 External APIC on SD Bus (disable XOE# for APIC cycles) ........................................always reads 0 1 Reserved 0 DMA Line Buffer Disable 0 DMA cycles can be to/from line buffer ....... def 1 Disable DMA Line Buffer -40- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B If the internal RTC is ...
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... Channel 6 Base Address Bits 15-4...........default = 0 3 Channel 6 Enable 0 Disable................................................... default 1 Enable 2-0 Reserved ........................................always reads 0 Offset 6F-6E - Distributed DMA Ch 7 Base / Enable .... RW 15-4 Channel 7 Base Address Bits 15-4...........default = 0 3 Channel 7 Enable 0 Disable................................................... default 1 Enable ........................................always reads 0 2-0 Reserved -41- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... Disable................................................... default 1 Enable 1 Internal APIC 0 Disable................................................... default 1 Enable 0 GPI0/IOCHCK, GPO[7-1]/LA[23-17] Select 0 GPI0, GPO[7-1]..................................... default 1 IOCHCK, LA[23-17] Bits 18-0 also control multi-function pin definitions. Refer to the General Purpose Inputs and Outputs sections of the pin descriptions for more information. -42- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... Enable 1 PCI DMA Channel 1 Enable 0 Disable ...................................................default 1 Enable 0 PCI DMA Channel 0 Enable 0 Disable ...................................................default 1 Enable Revision 0.3 June 17, 1999 Offset 80 – Programmable Chip Select Mask ................ RW 7-4 PCS1 I/O Port Address Mask bits 3-0 3-0 PCS0 I/O Port Address Mask bits 3-0 -43- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... Disable ...................................................default 1 Enable Revision 0.3 June 17, 1999 Offset 82 – ISA Positive Decoding Control 2 .................. RW 7 I/O Port Positive 6 5 1-0 -44- VT82C596B FDC Positive Decoding 0 Disable................................................... default 1 Enable LPT Positive Decoding 0 Disable................................................... default 1 Enable LPT Decode Range 00 3BCh-3BFh, 7BCh-7BEh ...................... default 01 378h-37Fh, 778h-77Ah 10 278h-27Fh, 678h-67Ah 11 -reserved- ...
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... Offset 84 – ISA Positive Decoding Control 4 .................. RW 7-4 Reserved ........................................always reads 0 3 FDC Decoding Range 0 Primary .................................................. default 1 Secondary 2 Sound Blaster Positive Decoding 0 Disable................................................... default 1 Enable 1-0 Sound Blaster Decode Range 00 220h-22Fh, 230h-233h .......................... default 01 240h-24Fh, 250h-253h 10 260h-26Fh, 270h-273h 11 280h-28Fh, 290h-293h -45- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... PLL PU 0 Enable.....................................................default 1 Disable 3 PLL Test Mode 0 Disable ...................................................default 1 Enable 2-0 PLL Test Mode Select Revision 0.3 June 17, 1999 Offset 89 – PLL Control ................................................... RW 7-4 Reserved ........................................always reads 0 3-2 PLL PCLK Input Delay Select 1-0 PLL CLK66 Feedback Delay Select -46- PCI Function 0 Registers - PCI-to-ISA Bridge VT82C596B ...
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... PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the function 1 PCI configuration space of the VT82C596B. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO Offset 3-2 - Device ID (0571h=IDE Controller) ...
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... Fixed at 0001b .................................................. fixed Revision 0.3 June 17, 1999 Offset 3C - Interrupt Line (0Eh) ..................................... RW Offset 3D - Interrupt Pin (00h) ......................................... RO 7-0 Interrupt Routing Mode 00h Legacy mode interrupt routing............... default 01h Native mode interrupt routing Offset 3E - Min Gnt (00h) ................................................. RO Offset 3F - Max Latency (00h).......................................... RO -48- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... Offset 42 - Reserved (Do Not Program) .......................... RW ........................................ always reads 0 7-2 Reserved 1-0 Reserved (Do Not Program).................... default = 0 Revision 0.3 June 17, 1999 Offset 43 - FIFO Configuration ....................................... RW 7-4 Reserved ........................................always reads 0 3-2 Threshold for Primary Channel 1/4 10 1/2 .................................................... default 11 3/4 1-0 Threshold for Secondary Channel 1/4 10 1/2 .................................................... default 11 3/4 -49- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... Max DRDY Pulse Width Maximum DRDY# pulse width after the cycle count. Command will deassert in spite of DRDY# status to avoid system ready hang limitation.......................................... default 01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks -50- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... Sec Clock Source 0 33 MHz.................................................. default 1 66 MHz 2 Reserved ........................................always reads 0 1-0 Sec Drive 1 Cycle Time Each byte defines UltraDMA operation for the indicated drive. The bit definitions are the same within each byte. -51- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... Than FIFO Size 0 Enabled...................................................default 1 Disabled Revision 0.3 June 17, 1999 Offset 61-60 - Primary Sector Size .................................. RW 15-12 Reserved ........................................ always reads 0 11-0 Number of Bytes Per Sector ................ default=200h Offset 69-68 - Secondary Sector Size .............................. RW 15-12 Reserved ........................................ always reads 0 11-0 Number of Bytes Per Sector ...def=200h (512 bytes) -52- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... Set Controller to Perform PIO Mode Data Port Prefetch 6 Set Controller to Perform PIO Mode Data Port Buffer Write 5 Set Controller to Perform DMA Mode Read Pipeline Operation 4 Set Controller to Perform DMA Mode Write Pipeline Operation 3 Stop S/G Bus Master 2-0 Reserved ........................................ always reads 0 -53- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... Refer to the SFF 8038I v1.0 specification for further details. I/O Offset 0 - Primary Channel Command I/O Offset 2 - Primary Channel Status I/O Offset 4-7 - Primary Channel PRD Table Address I/O Offset 8 - Secondary Channel Command I/O Offset A - Secondary Channel Status I/O Offset C-F - Secondary Channel PRD Table Address -54- Function 1 Registers - Enhanced IDE Controller VT82C596B ...
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... There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT82C596B. The USB I/O registers are defined in the UHCI v1.1 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID ....................................................... RO 0-7 Vendor ID ...
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... Set trap 60/64 status bits without checking enable bits 1 A20gate Pass Through Option 0 Pass through A20GATE command sequence defined in UHCI .................................... default 1 Don’t pass through Write I/O port 64 (ff) ........................................always reads 0 0 Reserved -56- Function 2 Registers - Universal Serial Bus Controller VT82C596B ...
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... Refer to the UHCI v1.1 specification for further details. I/O Offset 1-0 - USB Command I/O Offset 3-2 - USB Status I/O Offset 5-4 - USB Interrupt Enable I/O Offset 7-6 - Frame Number I/O Offset B-8 - Frame List Base Address I/O Offset 0C - Start Of Frame Modify I/O Offset 11-10 - Port 1 Status / Control I/O Offset 13-12 - Port 2 Status / Control I/O Offset 1F-14 - Reserved -57- Function 2 Registers - Universal Serial Bus Controller VT82C596B ...
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... Interface) Power Management VT82C596B which includes a System Management Bus (SMBus) interface controller. The power management system of the VT82C596B supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v1.0 specifications. PCI Configuration Space Header Offset 1-0 - Vendor ID ....................................................... RO 0-7 Vendor ID ...
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... RTC Enable Signal Gated with PSON (SUSC#) in Soft-Off Mode 0 Disable................................................... default 1 Enable 1 Clock Throttling Clock Selection 0 32 usec (512 usec cycle time) ................ default 1 1 msec (16 msec cycle time) 0 Reserved (Do Not Program) ...................... default = 0 -59- Function 3 Registers - Power Management and SMBus VT82C596B The ...
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... Ena/Disa IRQ6 as Secondary Intr Channel 5 1/0 = Ena/Disa IRQ5 as Secondary Intr Channel 4 1/0 = Ena/Disa IRQ4 as Secondary Intr Channel 3 1/0 = Ena/Disa IRQ3 as Secondary Intr Channel 2 Reserved ........................................always reads 0 1 1/0 = Ena/Disa IRQ1 as Secondary Intr Channel 0 1/0 = Ena/Disa IRQ0 as Secondary Intr Channel -60- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... Wait for CPU Stop Grant cycle -61- Reserved ........................................always reads 0 Internal Clock Stop for PCI Idle 0 Disable................................................... default 1 Enable Internal Clock Stop During C3 0 Disable................................................... default 1 Enable Internal Clock Stop During Suspend 0 Disable................................................... default 1 Enable Function 3 Registers - Power Management and SMBus VT82C596B ...
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... GP0 Timer Automatic Reload This bit is set to one to enable the GP0 timer to reload automatically after counting down to 0. 1-0 GP0 Timer Base 00 Disable................................................... default 01 1/16 second 10 1 second 11 1 minute Register (Power -62- Function 3 Registers - Power Management and SMBus VT82C596B Timer Reload Enable Register (Power ...
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... GPO8 Pin Function (Pin T19) 00 GPO8 (ACPI Rx4C[8] ...........................default Output Output Output Revision 0.3 June 17, 1999 Offset 55 – Wakeup Control ............................................ RW 7-1 Reserved ........................................always reads 0 0 USB Wakeup for STR / STD / Soft Off 0 Disable................................................... default 1 Enable -63- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... Code) may be changed by writing the desired value to this location. Register (Power Offset 63 - Base Class Read Value ................................... WO 7-0 Rx0B Read Value The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location. Register (Power -64- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... R/W for Shadow Port 1 0 Disable................................................... default 1 Enable Offset D5 – SMBus Slave Address for Port 2 ................. RW 7-1 SMBus Slave Address for Port 2...............default=0 0 R/W for Shadow Port 2 0 Disable................................................... default 1 Enable Offset D6 – SMBus Revision ID ....................................... RO 7-0 SMBus Revision Code -65- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... Reserved ........................................always reads 0 Slave Busy ......................................................... RO 0 SMBus controller slave interface is not processing data ...................................... default 1 SMBus controller slave interface is busy receiving data. None of the other SMBus registers should be accessed if this bit is set. Function 3 Registers - Power Management and SMBus VT82C596B ...
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... It is reset reads of the SMBus Host Control register (I/O Offset 2) and incremented automatically by each access to this register. The transfer of block data into (read) or out of (write) this storage array during an SMBus transaction always starts at index address 0. SMBUS Block Data ..................................default = 0 7-0 -67- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... SMBus master accesses to the host slave and slave shadow ports. 7-0 Shadow Command....................................default = 0 This field contains the command value which was received during an external SMBus master access whose address field matched the host slave address (10h) or one of the slave shadow port addresses. -68- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... SMBus Slave Data ....................................default = 0 This field contains the data value which was transmitted during an external SMBus master access whose address field matched one of the slave shadow port addresses or the SMBus host controller slave port address of 10h. -69- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... GBL_STS bit is set. ........................................always reads 0 Reserved Reserved ........................................always reads 0 ACPI Timer Enable (TMR_EN) ..............default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit generated when the TMR_STS bit is set. Function 3 Registers - Power Management and SMBus VT82C596B ...
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... S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then continues counting until the 14.31818 MHz input to the chip is stopped. If the clock is restarted without a reset, then the counter will continue counting from where it stopped. -71- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... Level 2 ........................................always reads 0 Reads from this register put the processor into the Stop Grant state (the VT82C596B asserts STPCLK# to suspend the processor). Wake up from Stop Grant state is by interrupt (INTR, SMI, and SCI). Reads from this register return all zeros; writes to this register have no effect ...
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... Enable SMI on setting of the XSMI2_STS bitdef=0 1 Enable SMI on setting of the PME_STS bit...def=0 0 Enable SMI on setting of the EXT_STS bit....def=0 These bits allow generation of an SMI using a separate set of conditions from those used for generating an SCI. -73- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... This bit may be set to trigger an SMI to be generated when the ST_TO_STS bit is set. 0 Primary Activity Enable (PACT_EN) ............def=0 This bit may be set to trigger an SMI to be generated when the PACT_STS bit is set. -74- Function 3 Registers - Power Management and SMBus VT82C596B ........................................always reads 0 ...
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... Revision 0.3 June 17, 1999 I/O Offset 2F - SMI Command (SMI_CMD) ................. RW 7-0 from suspend when -75- SMI Command Writing to this port sets the SW_SMI_STS bit. Note that if the SW_SMI_EN bit is set (see bit-6 of the Global Enable register at offset 2Ah), then an SMI is generated. Function 3 Registers - Power Management and SMBus VT82C596B ...
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... Don't set PACT_STS if PCI_STS is set....... def 1 Set PACT_STS if PCI_STS is set Note: Setting of any of the above bits also sets the PACT_STS bit (bit-0 of offset 28) which causes the GP0 timer to be reloaded (if PACT_GP0_EN is set) or generates an SMI (if PACT_EN is set). if the -76- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... I/O Offset 4B-48 - GPI Port Input Value (GPI_VAL) .... RO 31-22 Reserved ......................................... always read 0 21-0 GPI[21-0] Input Value ............................. Read Only I/O Offset 4F-4C - GPO Port Output Value (GPO_VAL) RW Reads from this register return the last value written (held on chip) 31 Reserved ........................................always reads 0 30-0 GPO[30-0] Output Value..........default = 7FFFFFFh -77- Function 3 Registers - Power Management and SMBus VT82C596B ...
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... Figure 6. Power Management Subsystem Block Diagram Refer to ACPI Specification v1.0 and APM specification v1.2 for additional information. Revision 0.3 June 17, 1999 Processor Bus States The VT82C596B supports the complete set processor states as specified in the Advanced Configuration and Power Interface (ACPI) specification (and defined in ACPI I/O space Registers 10-15): C0: ...
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... SUSA# and SUSB# asserted), and to STD (all three SUS# signals asserted). In particular, the assertion of SUSC# can be used to turn off the VCC supply to the VT82C596B. Two suspend status indicators (SUSST1-2#) are provided to inform the north bridge and the rest of the system of the processor and system suspend states ...
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... PCI Bus PCLK BIOS ROM Keyboard / Mouse Figure 7. Apollo MVP3 System Block Diagram Using the VT82C596B South Bridge Revision 0.3 June 17, 1999 3) Generic Global Events defined in the GBL_STS and System and Processor Resume Events Depending on the system suspend state, different features can be enabled to resume the system ...
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... Peripheral Events Primary and secondary events define system events in general and the response is typically expressed in terms of system events. Individual peripheral events can also be monitored by the VT82C596B through the GP1 timer. The following four categories of peripheral events are distinguished (via register GP_RLD_EN): Bit-7 ...
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... Tristate leakage current OZ I Power supply current CC Revision 0.3 June 17, 1999 E S LECTRICAL PECIFICATIONS Min 0 -55 -0.5 = 5V) -0 3.1 - 3.6V) -0.5 CC Min Max -0.50 2 0.45 2.4 - +/-10 - +/-20 - -82- Max Unit 125 5.5 Volts 5.5 Volts V + 0.5 Volts CC Unit Condition 0 =4.0mA =-1.0mA OH uA 0<V < 0.45<V <V OUT Electrical Specifications VT82C596B ...
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... PREQ# Valid Delay from PCLK Rising VD T FRAME#,TRDY#,IRDY# Float Delay from PCLK Rising FD T CBE[3:0]#, STOP#,DEVSEL# Float Delay from PCLK Rising FD Revision 0.3 June 17, 1999 Table 6. AC Characteristics - PCI Cycle Timing Parameter -83- VT82C596B Min Max Unit Notes ...
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... Delay time of PCLK to DIOR Data setup time during PIO write WDS T Data hold time during PIO write WDH T Data setup time during PIO read RDS T Data hold time during PIO read RDH Revision 0.3 June 17, 1999 -84- VT82C596B Timing Unit 29.3 ns 1.1 ns 2.3 ns 29.3 ns 42.2 ns 17 ...
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... DDRQ (Drive) DDACK# (Host) STOP (Host) DDMARDY# (Drive) HSTROBE (Host) DDMARDY# (Drive) HSTROBE (Host) Data Figure 9. UltraDMA-33 IDE Timing - Drive Initiating Burst for Write Command Revision 0.3 June 17, 1999 ENV1 LI1 T DS1 T DH1 ENV2 -85- VT82C596B DVH2 T DVS2 Electrical Specifications ...
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... DDRQ (Drive) DDACK# (Host) For Write: DDMARDY# (Drive) HSTROBE (Host) For Read: STOP (Host) HDMARDY# (Host) Figure 10. UltraDMA-33 IDE Timing - Pausing a DMA Burst Revision 0.3 June 17, 1999 T RFS T RP -86- VT82C596B Electrical Specifications ...
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... Figure 11. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Read Command DDRQ (Drive) DDACK# (Host) STOP (Host) DDMARDY# (Host) HSTROBE (Host) Data Figure 12. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Write Command Revision 0.3 June 17, 1999 T LI4 CRC T T DVS4 ZA4 T LI5A T MLI5 T LI5B CRC T DVS5 -87- VT82C596B T DVH4 T DVH5 Electrical Specifications ...
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... Figure 13. UltraDMA-33 IDE Timing - Host Terminating DMA Burst During Read Command DDRQ (Drive) DDACK# (Host) STOP (Host) HSTROBE# (Host) Data Figure 14. UltraDMA-33 IDE Timing - Host Terminating DMA Burst During Write Command Revision 0.3 June 17, 1999 T MLI6 T ZA6 CRC T MIL7 T LI7 T T DVS7 CRC -88- VT82C596B DVH7 Electrical Specifications ...
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... T 2 DCS3# / DCS1# DA [2: DIOW# DD Write DIOR# DD Read Figure 15. UltraDMA-33 IDE Timing - PIO Cycle Revision 0.3 June 17, 1999 WDS WDH RDH RDS -89- VT82C596B Electrical Specifications ...
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... Figure 16. Mechanical Specifications - 324-Pin Ball Grid Array Package Revision 0.3 June 17, 1999 M S ECHANICAL PECIFICATIONS 24.00 Ref -90- VT82C596B Ø 1.00 (3X) Ref. ø0.75±0.15(324X) ø0. ø0. ...