RS8973EPF Mindspeed Technologies, RS8973EPF Datasheet
RS8973EPF
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RS8973EPF Summary of contents
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Preliminary Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. RS8973 Single-Chip SDSL/HDSL Transceiver The RS8973 is a full-duplex 2B1Q transceiver based on Conexant’s HDSL technology, with a ...
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... Ordering Information Model Number RS8973EPF Information provided by Conexant Systems, Inc. (Conexant) is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products ...
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Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.2.5 Echo Canceller 2.2.5.1 Linear Echo Canceller 2.2.5.2 Nonlinear Echo Canceller (NEC ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 3.0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 0x32, 0x33—Far-End Low Alarm Threshold Register (far_end_low_alarm_th_low, far_end_low_alarm_th_high) 0x34, 0x35—SNR Alarm Threshold Register (snr_alarm_th_low, snr_alarm_th_high) 0x36, 0x37—Cursor Level Register (cursor_level_low, cursor_level_high) 0x38, 0x39—DAGC Target Register (dagc_target_low, dagc_target_high) 0x3A—Symbol Detector Modes Register (detector_modes) 0x3B—Peak Detector Delay Register (peak_detector_delay) ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 4.3 Voltage Reference and Compensation Circuitry 4.4 Crystal/Clock Interface 5.0 Electrical and Mechanical Specifications 5.1 Absolute Maximum Ratings 5.2 Recommended Operating Conditions 5.3 Electrical Characteristics 5.4 Clock Timing . . . . . . . . ...
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Table of Contents viii Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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RS8973 Single-Chip SDSL/HDSL Transceiver List of Figures Figure 1-1. HDSL T1/E1 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures x Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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RS8973 Single-Chip SDSL/HDSL Transceiver List of Tables Table 1-1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables xii Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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System Overview 1.1 Functional Summary The RS8973 High-bit-rate Digital Subscriber Line (HDSL) transceiver is an integral component of Conexant's HDSL chipset. System performance of the chipset allows 2-pair T1, 1-pair E1, 2-pair E1, and 3-pair E1 transmission. With its ...
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System Overview 1.1 Functional Summary The RS8973 comprises five major functions: a transmit section, a receive section, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. between each of these functional blocks. Figure ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 1.1.1 Transmit Section The source of transmitted symbols is programmable through the microcomputer interface. The primary choices include external 2B1Q-encoded data presented to the TQ[1,0]/TDAT pins of the channel unit interface, internally looped-back receive symbols from ...
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System Overview 1.1 Functional Summary 1.1.3 Timing Recovery and Clock Interface The clock interface includes a crystal amplifier and a clock synthesizer module to reduce the external components needed for clock generation. The crystal frequency should be 10.24 MHz. ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 1.2 Pin Descriptions The RS8973 is packaged in a 100-pin plastic quad flat pack (PQFP). The pin assignments are shown in are listed in Figure 1-3. Pin Diagram VDD1 RD/DS WR/R/W ALE IRQ READY AD[0] AD[1] ...
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System Overview 1.2 Pin Descriptions Table 1-1. Pin Descriptions Pin Pin I/O Pin Label 1 VDD1 – RD/ WR/R ALE IRQ ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Signal definitions are provided in column analog output OD = open-drain output analog input I/O = bidirectional connect Table 1-2. Hardware Signal Definitions ( Pin ...
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System Overview 1.2 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name I/O RST Reset RQ[1]/ Receive Quat 1/ O RDAT Receive Data RQ[0]/ BCLK Receive Quat 0/ Bit O Clock TQ[1]/ TDAT Transmit ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name I/O TBCLK Transmit Baud-Rate Clock RBCLK Receive Baud-Rate Clock TXP, TXN Transmit Positive, OA Negative RXP, RXN Receive Positive, IA Negative RXBP, RXBN Receive ...
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System Overview 1.2 Pin Descriptions Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name I/O TDI JTAG Test Data Input TMS JTAG Test Mode Select TDO JTAG Test Data O Output TCK JTAG Test Clock Input ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 1.3 Regenerator Configuration Figure 1-4 regenerator system. Bt8953A/RS8953B provides an internal cross-connect data path between REG-R and REG-C. Figure 1-4. Regenerator System Block Diagram REG–R RS8973 To COT HCLK (35) XTALO (39) XTALI/MCLK (40) 10.24 MHz ...
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System Overview 1.3 Regenerator Configuration 1-12 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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Functional Description 2.1 Transmit Section The transmit section block diagram is shown in major functions: a symbol source selector/scrambler, a variable gain digital-to-analog converter (DAC), a pulse-shaping filter, an analog CT reconstruction filter, and a line driver. Figure 2-1. ...
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Functional Description 2.1 Transmit Section 2.1.1 Symbol Source Selector/Scrambler The input source selector/scrambler can be configured through the Transmitter Modes Register [transmitter_modes; 0x0B] data_source [2:0] bits. It selects the source of the data to be transmitted and determines whether ...
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RS8973 Single-Chip SDSL/HDSL Transceiver In two-level mode, the magnitude bit is forced This forces the symbols and – shown in Table 2-3. Two-Level Bit-to-Symbol Conversions The scrambler is essentially a 23-bit-long ...
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Functional Description 2.1 Transmit Section 2.1.3 Pulse-Shaping Filter The pulse-shaping filter is used to filter the quats output from the variable-gain DAC. This filter, when combined with other filtering in the signal path, produces a transmitted signal on the ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.2 Receive Section Like the transmit section, the receive section consists of both analog and digital circuitry. The VGA provides the interface to the analog signals received from the line and the hybrid. The ADC then ...
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Functional Description 2.2 Receive Section 2.2.3 Digital Signal Processor The DSP includes five Least Mean Squared (LMS) filters: • Echo Canceller (EC) • Digital Automatic Gain Controller (DAGC) • Feed Forward Equalizer (FFE) • Error Predictor (EP) • Decision ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.2.3.1 Digital Prior to the main signal processing, the input signal must be adjusted for any DC Front-End offset. The front-end module also monitors the input signal level, which includes measuring DC and AC input signal ...
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Functional Description 2.2 Receive Section 2.2.3.2 Offset A nonzero DC level on the input can be corrected offset value Adjustment [dc_offset_low, dc_offset_high; 0x26, 0x27], which is subtracted from the input. The DC offset is a 16-bit ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.2.5 Echo Canceller The echo canceller (EC) removes images of the transmitted symbols from the received signal and consists of two blocks: a linear and nonlinear echo canceller. The organization of the blocks is displayed in ...
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Functional Description 2.2 Receive Section 2.2.6.2 Feed Forward The feed forward equalizer (FFE) removes precursors from the received signal. Equalizer The FFE can be operated in a special adapt last mode. In this mode, which is useful during startup, ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.2.7.4 Scrambler The scrambler can operate as either a scrambler descrambler. The Module scrambler block is used during the scrambled-1s part of the start-up sequence. This provides an error-free signal for equalizer adaptation. ...
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Functional Description 2.2 Receive Section 2.2.7.5 Sync Detector The sync detector compares the output of the scrambler with the output of the symbol detector. The number of equivalent bits is accumulated for 128 comparisons. The result is then compared ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.3 Timing Recovery and Clock Interface The timing recovery and clock interface block consists of the timing recovery circuit, the crystal amplifier, and the clock synthesizer, as detailed in The main purpose of this circuitry is ...
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Functional Description 2.3 Timing Recovery and Clock Interface Figure 2-5. Timing Recovery and Clock Interface Block Diagram 2-14 Single-Chip SDSL/HDSL Transceiver Phase Detector Control Meter Register Registers [0x40, 0x41] Detected Timing Symbol Recovery Circuit Equalizer Error Clock Synthesizer Crystal ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.3.1 Timing Recovery Circuit The timing recovery circuit uses the RS8973’s internal detected symbol and equalizer error signals to regenerate the received data symbol clock (QCLK). The HCLK output is synchronized with the edges of the ...
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Functional Description 2.4 Channel Unit Interface 2.4 Channel Unit Interface The quaternary signals of the channel unit interface have four modes which are programmable through bits 0 and 1 of the Channel Unit Interface Modes Register [cu_interface_modes; 0x06]. They ...
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RS8973 Single-Chip SDSL/HDSL Transceiver The parallel slave mode uses RBCLK and TBCLK inputs to synchronize data transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the use of two internal FIFOs allows an arbitrary phase relationship to QCLK. TQ[1] ...
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Functional Description 2.5 Microcomputer Interface 2.5 Microcomputer Interface The microcomputer interface provides operational mode control and status through internal registers. A microcomputer write sets the operating modes to the appropriate registers. A read to a register verifies the operating ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 2.5.2.1 RAM Access The internal RAM of the scratch pad, LEC, NEC, DFE, equalizer, and microcode Registers are accessed indirectly. They all share a common data register which is used for both read and write operations: ...
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Functional Description 2.5 Microcomputer Interface 2.5.4 Reset The reset input (RST active-low input that places the transceiver in an inactive state by setting the mode bit (0) in the Global Modes and Status Register [global_modes; 0x00]. An ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Table 2-6. Timers Startup Timer 1 Startup Timer 2 Startup Timer 3 Startup Timer 4 SNR Alarm Timer General Purpose Timer 3 General Purpose Timer 4 Four timers are provided for use in timing start-up events. ...
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Functional Description 2.6 Test and Diagnostic Interface (JTAG) 2.6 Test and Diagnostic Interface (JTAG) To access individual chips for PCB verification, special circuitry is incorporated within the transceiver, which complies with IEEE Std 1149.1-1990, Standard Test Access Port and ...
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Registers 3.1 Conventions Unless otherwise noted, the following conventions apply to all applicable register descriptions: • For storage of multiple-bit data fields within a single byte-wide register, • If only a single data field is stored in a byte-wide ...
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Registers 3.2 Register Summary 3-2 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD Conexant Preliminary Information 3.0 Registers 3.2 Register Summary 3-3 ...
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Registers 3.2 Register Summary 3-4 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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RS8973 Single-Chip SDSL/HDSL Transceiver N8973DSD Conexant Preliminary Information 3.0 Registers 3.2 Register Summary 3-5 ...
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Registers 3.2 Register Summary 3-6 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 3 3.3 Register Description 0x00—Global Modes and Status Register (global_modes hw_revision[3] hw_revision[2] hw_revision[1] Chip Revision Number—Read-only unsigned binary field encoded with the chip revision hw_revision[3:0] number. Smaller values represent earlier versions, while larger ...
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Registers 3.3 Register Description 0x01—Serial Monitor Source Select Register (serial_monitor_source hclk_freq[1] hclk_freq[0] smon[5] HCLK Frequency Select—Read/write binary field selects the frequency of the HCLK output. hclk_freq[1,0] hclk_freq[1] hclk_freq[ Serial Monitor Source Select—Read/write ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x02—Interrupt Mask Register Low (mask_low_reg) Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A logical 1 represents the masked condition. A logical 0 represents the unmasked condition. All mask ...
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Registers 3.3 Register Description 0x04—Timer Source Register (timer_source) Independent read/write (zero only) interrupt flags, one for each of eight internal timers. Each flag bit is set and stays set when its corresponding timer value transitions from ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x06—Channel Unit Interface Modes Register (cu_interface_modes — — — Transmit Baud Clock Polarity—Read/write control bit defines the polarity of the TBCLK tbclk_pol input while in the parallel slave interface mode. When tbclk_pol is ...
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Registers 3.3 Register Description 0x07—Receive Phase Select Register (receive_phase_select — imp_short[2] imp_short[1] Impulse Shortening Filter—Read/write binary field that determines the coefficient of the imp_short[2:0] impulse shortening filter. It must be set per the software provided by ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0] Negate Symbol—Read/write control bit which, when set, inverts (2s complement) the receive negate_symbol signal path at the output of the nonlinear echo canceller. ...
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Registers 3.3 Register Description 0x0B—Transmitter Modes Register (transmitter_modes — isolated_pulse[1] isolated_pulse[0] Isolated Pulse Level Select—Read/write binary field that selects one of four output pulse isolated_pulse[1,0] levels while in the isolated pulse or alternating symbol transmitter mode. ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x0C—Timer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For the ...
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Registers 3.3 Register Description 0x0E—Timer Continuous Mode Register (timer_continuous) Independent read/write mode bits, one for each of the eight internal timers. When any individual bit is set, the corresponding timer is placed in the continuous count mode. While in ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x14, 0x15—Startup Timer 3 Interval Register (sut3_low, sut3_high) A 2-byte read/write register that stores the countdown interval for Startup Timer 3 in unsigned binary format. Each increment represents 1024 symbol periods. The contents of this register ...
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Registers 3.3 Register Description 0x20—Clock Frequency Select Register (clock_freq_select clk_freq[7] clk_freq[6] clk_freq[5] Read/write binary field, which along with clk_freq[9,8] of the PLL Modes Register (0x22), clk_freq[7:0] specifies the data rate used by the clock synthesizer to ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Switch Cap Pole Control—Read/write control bit, specifies the pulse shaping filter switch_cap_pole characteristics. When switch_cap_pole is set, it enables output pulse shape conforming to ETSI specifications for 2320 kbps operation. When reset, it enables output pulse ...
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Registers 3.3 Register Description 0x23—Test Register (test_reg23) A 3-byte read/write register used for device testing by Conexant. This register is automatically initialized to 0x000000 upon RST assertion and initial power application. This register must be initialized according to the ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x29—Transmitter Gain Register (tx_gain — — tx_gain[3] Transmit Gain—A 4-bit, 2s-complement, read/write field controlling the transmitter gain. tx_gain[3:0] Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] can be written into ...
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Registers 3.3 Register Description 0x2E—Scrambler Synchronization Threshold Register (scr_sync_th) A 7-bit read/write register representing an unsigned binary number. The contents of this register are used to test for scrambler synchronization during the automatic-scrambler synchronization mode of the symbol detector. ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x3A—Symbol Detector Modes Register (detector_modes enable_peak_ output_mux_ output_mux_ detector control[1] control[0] enable_peak_ Enable Peak Detector—Read/write control bit that enables the peak detection function when detector set; disables the function when cleared. When enabled, ...
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Registers 3.3 Register Description LFSR Lock—Read/write control bit that enables the auto-scrambler synchronization mode lfsr_lock (lfsr_lock) in the detector when set and disables this mode when cleared. Affects the behavior of the scrambler/descrambler function, overriding the descr_on setting. When ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x3C—Digital AGC Modes Register (dagc_modes — — — eq_error_ Equalizer Error Adaptation—Read/write control bit that selects between the equalizer-error adaptation adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error adaptation ...
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Registers 3.3 Register Description 0x3E—Error Predictor Modes Register (ep_modes — — — Zero Output—Read/write control bit that, when set, zeros the error predictor correction signal zero_output before subtraction at the slicer. Achieves the affect of disabling, ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x44, 0x45—DC Level Meter Register (dc_meter_low, dc_meter_high) A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2s-complement DC-level meter accumulator. This meter sums the value of the receive signal input path—after DC offset correction ...
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Registers 3.3 Register Description 0x4A, 0x4B—Noise Level Histogram Meter Register (noise_histogram_low, noise_histogram_high) A 2-byte read-only register containing all 16 bits of the unsigned noise-level histogram meter accumulator. This meter counts the number of high-noise-level conditions which occur during each ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x50, 0x51—Noise Level Meter Register (nlm_low, nlm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This meter sums the absolute value of the detector’s slicer-error signal over each Meter Timer ...
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Registers 3.3 Register Description 0x72—NEC Read Tap Select Register (nonlinear_ec_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range decimal. When written, this register causes the selected 14-bit coefficient of the ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x76—Scratch Pad Read Tap Select (sp_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range decimal. When written, this register causes the selected 8-bit scratch pad memory location ...
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Registers 3.3 Register Description 0x78—Equalizer Read Select Register (eq_add_read) A 6-bit read/write register representing an unsigned binary address defined over a range decimal. When written, this register causes the selected 16-bit location of the equalizer ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 0x79—Equalizer Write Select Register (eq_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range decimal. When written, this register causes the lowest-order 16 bits of the Access Data ...
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Registers 3.3 Register Description 3-34 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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Interconnection Information NOTE: The configuration described in this section supports data rates ranging from 144 kbps and 2320 kbps, with the output signal conforming to ETS TS 101 135 (formerly ETR 152) specifications for pulse-shape, power spectral density and ...
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Interconnection Information 4.1 Transmission Line Interface 4.1 Transmission Line Interface The transmission line interface consists of the compromise hybrid, two impedance matching resistors and the line transformer. Interconnection Figure 4-1. Line Interface Interconnection Diagram Antialiasing Filter RXP (77) C5 ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 4.1.1 Compromise Hybrid The purpose of the compromise hybrid is to model the impedance of the transmission line. This model generates an approximation of the transmitted signal’s echo. The echo replica is then subtracted from the ...
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Interconnection Information 4.1 Transmission Line Interface 4.1.2 Impedance-Matching Resistors Impedance-matching resistors are placed in the transmit path so that the output impedance of the line interface more closely matches the impedance of the transmission line and load. This maximizes ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Table 4-3. Line Transformer Specifications Parameter (1) Turns Ratio Primary Inductance Return Loss (mid-band) Return Loss (low-band) Return Loss (high-band) Longitudinal Balance (low-band) Longitudinal Balance (high band) Insertion Loss Frequency Response Total Harmonic Distortion NOTE(S): (1) ...
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Interconnection Information 4.2 DC Blocking Capacitor 4.2 DC Blocking Capacitor A DC blocking capacitor is placed in series with the center split primary winding (line side) of the line transformer to facilitate remote power feed or injection of sealing ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 4.4 Crystal/Clock Interface A crystal or an external clock is needed to provide a reference clock for the RS8973 crystal is used, it must be connected to the XTALI/MCLK and XTALO pins along with ...
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Interconnection Information 4.4 Crystal/Clock Interface 4-8 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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Electrical and Mechanical Specifications 5.1 Absolute Maximum Ratings Stresses above those listed in device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed in the operational sections of ...
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Electrical and Mechanical Specifications 5.2 Recommended Operating Conditions 5.2 Recommended Operating Conditions The recommended operating conditions are described in Table 5-2. Recommended Operating Conditions Symbol Parameter V Digital core-logic supply voltage DD1 V Digital I/O-buffer supply voltage DD2 V ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 5.3 Electrical Characteristics Typical characteristics measured at nominal operating conditions: • T • V • V Minimum/maximum characteristics guaranteed over extreme operating conditions: • Min • Min The parameters of the electrical characteristics are displayed in ...
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Electrical and Mechanical Specifications 5.3 Electrical Characteristics Table 5-3. Electrical Characteristics Symbol Parameter V High-Level Output Voltage @ Low-Level Output Voltage @ I OLL OL V Low-Level Output Voltage @ Input ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 5.4 Clock Timing Tables 5-4 characteristics. clock control timing, respectively. Table 5-4. MCLK Timing Requirements Symbol Parameter 1 MCLK Period (1) 2 MCLK Pulse-Width Low 3 MCLK Pulse-Width High NOTE(S): ( external clock is ...
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Electrical and Mechanical Specifications 5.4 Clock Timing Table 5-6. QCLK Switching Characteristics Symbol Parameter 9 QCLK period (T ) (1) QCLK 10 QCLK pulse-width high 11 QCLK pulse-width low 12 QCLK hold after HCLK rising edge 13 QCLK delay ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 5.5 Channel Unit Interface Timing Tables 5-7 switching characteristics. timing in parallel master mode, parallel slave mode, and serial mode, respectively. Table 5-7. Channel Unit Interface Timing Requirements, Parallel Master Mode Symbol 14 TQ[1,0] setup prior ...
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Electrical and Mechanical Specifications 5.5 Channel Unit Interface Timing Table 5-9. Channel Unit Interface Timing Requirements, Parallel Slave Mode Symbol 18 TBCLK, RBCLK Period (1) 19 TBCLK RBCLK Pulse-Width High , 20 TBCLK RBCLK Pulse-Width Low , 21 TQ[1,0] ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-4. Channel Unit Interface Timing, Parallel Slave Mode TBCLK and RBCLK polarities are programmable through the CU Interface Modes Register. The figure depicts both NOTE(S): clocks programmed to falling-edge active. Table 5-11. Channel Unit Interface ...
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Electrical and Mechanical Specifications 5.5 Channel Unit Interface Timing Figure 5-5. Channel Unit Interface Timing, Serial Mode HCLK 31 30 BCLK 33 32 QCLK RDAT 25 TDAT 5-10 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 29 ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 5.6 Microcomputer Interface Timing Tables 5-13 and switching characteristics, respectively. write and read timing. Table 5-13. Microcomputer Interface Timing Requirements Symbol Parameter 34 ALE pulse-width high 35 Address setup prior to ALE falling edge 36 (1) ...
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Electrical and Mechanical Specifications 5.6 Microcomputer Interface Timing Table 5-14. Microcomputer Interface Switching Characteristics Symbol Parameter 49 Data out enable (Low Z) after Read Strobe falling edge 50 Data out valid after Read Strobe low 51 Data out hold ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-6. MCI Write Timing, Intel Mode (MOTEL = 0) AD[7:0] Address or ADDR[7: Write Strobe 34 ALE READY N8973DSD 5.0 Electrical and Mechanical Specifications Data (Input ...
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Electrical and Mechanical Specifications 5.6 Microcomputer Interface Timing Figure 5-7. MCI Write Timing, Motorola Mode (MOTEL = 1) AD[7:0] or Address ADDR[7: Write Strobe R/W 34 ALE READY Figure 5-8. MCI Read Timing, Intel Mode (MOTEL = ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-9. MCI Read Timing, Motorola Mode (MOTEL = 1) AD[7:0] Address or ADDR[7: Read Strobe R/W 34 ALE READY N8973DSD 5.0 Electrical and Mechanical Specifications Data (Output ...
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Electrical and Mechanical Specifications 5.6 Microcomputer Interface Timing Figure 5-10. Internal Write Timing Write Strobe IRQ Internal Register Internal RAM Access Data Register 5-16 Single-Chip SDSL/HDSL Transceiver Conexant Preliminary Information RS8973 N8973DSD ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 5.7 Test and Diagnostic Interface Timing Tables 5-15 switching characteristics. SMON timing, respectively. Table 5-15. Test and Diagnostic Interface Timing Requirements Symbol 63 TCK pulse-width high 64 TCK pulse-width low 65 TMS, TDI setup prior to ...
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Electrical and Mechanical Specifications 5.7 Test and Diagnostic Interface Timing Table 5-16. Test and Diagnostic Interface Switching Characteristics Symbol 67 TDO hold after TCK falling edge (1) 68 TDO delay after TCK low (1) 69 TDO enable (Low Z) ...
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RS8973 Single-Chip SDSL/HDSL Transceiver 5.8 Analog Specifications Tables 5-17 specifications. two- and three-pair systems. template for one-pair systems. bound of the average PSD of 392, 584, and 1160 kbaud systems, respectively. Table 5-17. Receiver Requirements and Specifications Parameter Input signals ...
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Electrical and Mechanical Specifications 5.8 Analog Specifications Table 5-18. Transmitter Analog Requirements and Specifications ( Parameter (1, 2, 3,4) See Figures Power spectral density R = 135 L Average power ( ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Table 5-19. Transmit Pulse Template for Two- and Three-Pair Systems (Source ETSI TS 101 135 Formerly ETR 152) Normalized Level A 0.01 0.0264 B 1.07 2.8248 C 1.00 2.6400 D 0.93 2.4552 E 0.03 0.0792 F ...
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Electrical and Mechanical Specifications 5.8 Analog Specifications Figure 5-14. Transmit Pulse Template for One-Pair Systems (Source ETSI TS 101 135 Formerly ETR 152) – 0, 0,93 – 1, ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-15. Upper Bound of the Average PSD of a 392 kbaud System (Source ETSI TS 101 135 Formerly ETR 152) dBm/Hz – 20 – 40 – 60 – 80 – 100 – 120 1 e3 ...
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Electrical and Mechanical Specifications 5.9 Test Conditions Figure 5-17. Upper Bound of the Average PSD of a 1160 kbaud System (Source ETSI TS 101 135 Formerly ETR 152) dBm/Hz – 20 – 41,5 dBm/Hz – 40 – 60 – ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-19. Standard Output Load (Totem Pole and Three-State Outputs) Figure 5-20. Open-Drain Output Load (IRQ) N8973DSD 5.0 Electrical and Mechanical Specifications IOL From RS8973 CL IOH I OD From RS8973 C L Conexant Preliminary Information ...
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Electrical and Mechanical Specifications 5.10 Timing Measurements 5.10 Timing Measurements Figure 5-21 waveforms. Figure 5-21. Input Waveforms for Timing Tests 3 V Input High Figure 5-22. Output Waveforms for Timing Tests VDD 2.4 V Output High 5-26 Single-Chip SDSL/HDSL ...
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RS8973 Single-Chip SDSL/HDSL Transceiver Figure 5-23. Output Waveforms for Three-state Enable and Disable Tests 1.5 V Output Disabled N8973DSD 5.0 Electrical and Mechanical Specifications V – 0 1 Output Output ...
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Electrical and Mechanical Specifications 5.11 Mechanical Specifications 5.11 Mechanical Specifications Figure 5-24. 100-Pin PQFP TOP VIEW 5-28 Single-Chip SDSL/HDSL Transceiver BOTTOM VIEW 1.60 REF. (.063) Conexant Preliminary Information RS8973 D1 ...
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Appendix A: Acronym List The following list of acronyms and abbreviations does not include all signal, register, and bit names. N8973DSD A A ADC analog-to-digital converter AGC automatic gain control B BDSL Boundary Scan Description Language BER bit error rate ...
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Appendix A : Acronym List A-2 J JTAG Joint Test Action Group L LEC Linear Echo Canceller LMS least mean square LSB least significant bit M MCI microcomputer interface MSB most significant bit N NEC nonlinear echo canceller P PCB ...
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Further Information Hong Kong literature@conexant.com Phone: (852) 2827 0181 1-800-854-8099 (North America) Fax: (852) 2827 6488 33-14-906-3980 (International) India Web Site Phone: (91 11) 692 4780 www.conexant.com Fax: (91 11) 692 4712 World Headquarters Korea Conexant Systems, Inc. Phone: (82 ...