HI-8582PQI Holt Integrated Circuits, Inc., HI-8582PQI Datasheet

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HI-8582PQI

Manufacturer Part Number
HI-8582PQI
Description
Manufacturer
Holt Integrated Circuits, Inc.
Datasheet
GENERAL DESCRIPTION
The HI-8582/HI-8583 from Holt Integrated Circuits are a
silicon gate CMOS devices for interfacing a 16-bit parallel
data bus directly to the ARINC 429 serial bus. The
HI-8582/HI-8583 design offers many enhancements to the
industry standard HI-8282 architecture. The device
provides two receivers each with label recognition, 32 by
32 FIFO, and analog line receiver. Up to 16 labels may be
programmed for each receiver. The independent transmit-
ter has a 32 X 32 FIFO and a built-in line driver. The status
of all three FIFOs can be monitored using the external
status pins, or by polling the HI-8582/HI-8583 status
register. Other new features include a programmable
option of data or parity in the 32nd bit, and the ability to
unscramble the 32 bit word. Also, versions are available
with different values of input resistance and output
resistance to allow users to more easily add external
lightning protection circuitry. The device can be used at
nonstandard data rates when an option pin,
invoked.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-8582/HI-8583 apply the ARINC protocol to the
receivers and transmitter. Timing is based on a 1 Mega-
hertz clock.
Although the line driver shares a common substrate with
the receivers, the design of the physical isolation does not
allow parasitic crosstalk, and thereby achieves the same
isolation as common hybrid layouts.
APPLICATIONS
(DS8582 Rev. N)
March 2007
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Avionics data communication
Serial to parallel conversion
Parallel to serial conversion
HOLT INTEGRATED CIRCUITS
NFD
www.holtic.com
, is
HI-8582, HI-8583
FEATURES
PIN CONFIGURATION
BD15 - 9
BD14 - 10
BD12 - 12
BD13 - 11
BD11 - 13
D/R2
EN1
EN2
HF1
HF2
SEL - 6
FF1
FF2
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- 1
- 2
- 3
- 4
- 5
- 7
- 8
ARINC specification 429 compatible
Analog line driver and receivers connect
Dual receiver and transmitter interface
directly to ARINC bus
Programmable label recognition
On-chip 16 label memory for each receiver
32 x 32 FIFOs each receiver and transmitter
Independent data rate selection for
transmitter and each receiver
Status register
Data scramble control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & full military temperature ranges
52 - Pin Plastic Quad Flat Pack (PQFP)
(See page 14 for additional pin configuration)
HI-8582PQT
HI-8583PQT
HI-8582PQI
HI-8583PQI
System on a Chip
&
ARINC 429
(Top View)
39 - N/C
38 -
37 - ENTX
36 - V+
35 - TXBOUT
34 - TXAOUT
33 - V-
32 -
31 -
30 - TX/R
29 -
28 -
27 - BD00
CWSTR
FFT
HFT
PL2
PL1
03/07

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HI-8582PQI Summary of contents

Page 1

... BD12 - 12 BD11 - Pin Plastic Quad Flat Pack (PQFP) (See page 14 for additional pin configuration) HOLT INTEGRATED CIRCUITS www.holtic.com ARINC 429 System on a Chip (Top View N CWSTR 37 - ENTX HI-8582PQI 35 - TXBOUT HI-8582PQT 34 - TXAOUT & FFT HI-8583PQI 31 - HFT HI-8583PQT ...

Page 2

... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Transmitter FIFO Half Full Transmitter FIFO Full -9 ...

Page 3

... Unscramble ARINC data HI-8582, HI-8583 STATUS REGISTER The HI-8582/HI-8583 contain a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are is pulsed low. The output on BD00 - BD08 when the SEL = 0 ...

Page 4

... Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register ...

Page 5

... CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation ...

Page 6

... PL2 the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then words, each bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FIFO ignores further attempts to load data ...

Page 7

... The parity generator counts the Ones in the 31-bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. Setting CR4 to a Zero bypasses the parity generator, and allows 32 bits of data to be transmitted. ...

Page 8

... BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t ENDATA DATA BUS PL1 PL2 TX/R, HFT FFT , DATA BUS CWSTR HI-8582, HI-8583 DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN ...

Page 9

... PL t CWSTR CWSTR EN1 or EN2 t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-8582, HI-8583 STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 ...

Page 10

... TXBOUT) 10% one level BIT 32 RIN D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX TXAOUT TXBOUT HI-8582, HI-8583 TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 2 BIT 1 +5V -5V +5V - +10V 90 10% rx 90% ...

Page 11

... Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HI-8582, HI-8583 Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/ C Ceramic J-LEAD CERQUAD ...... 1.0 W, derate 7mW/ DC Current Drain per pin .............................................. ± ...

Page 12

... RIN1B, RIN2A to RIN2B GND Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source I IL NFD Pin One or zero V No load and magnitude at pin, ...

Page 13

... Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX LOW LINE DRIVER OUTPUT TIMING Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed Line driver transition differential times: (High Speed, control register CR13 = Logic 0) (Low Speed, control register CR13 = Logic 1) ...

Page 14

... ADDITIONAL HI-8582 / HI-8583 PIN CONFIGURATIONS BD15 - 16 BD14 - 17 BD13 - 18 BD12 - 19 BD11 - 20 ORDERING INFORMATION HI - 85xx HI-8582, HI-8583 FF1 - 8 HF1 - 9 D/ FF2 - 11 HF2 - 12 HI-8582CJI SEL - 13 HI-8582CJT EN1 - 14 & EN2 -15 HI-8583CJI HI-8583CJT 52 - Pin Cerquad J-lead (See page 1 for additional pin configuration) INPUT SERIES RESISTANCE ...

Page 15

... HI-8582 / HI-8583 PACKAGE DIMENSIONS 52-PIN J-LEAD CERQUAD 7 8 .019 .002 (.483 .051) 52-PIN PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .084 .013 ± (2.13 ± .32) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) ...

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