A1415A Actel Corporation, A1415A Datasheet
A1415A
Available stocks
Related parts for A1415A
A1415A Summary of contents
Page 1
... Notes: 1. One flip-flop per S-Module, two flip-flops per I/O-Module. 2. See product plan on page 1-178 for package availability. 3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3. 4. Clock-to-Output + Setup 199 7 © 1997 Actel Corporation • Replaces up to twenty 32 macro-cell CPLDs • Replaces up to one hundred 20-pin PAL • ...
Page 2
Des crip tion Actel’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity programmable logic device. ACT 3 FPGAs offer a high perfomance, PCI compliant programmable solution capable of 250 MHz on-chip performance and 7.5 nanosecond clock-to-output, with ...
Page 3
... Or der ing Info A14100 A – Die Revision Part Number A1415A = 1500 Gates A14V15A = 1500 Gates (3.3V) A1425A = 2500 Gates A14V25A = 2500 Gates (3.3V) A1440A = 4000 Gates A14V40A = 4000 Gates (3.3V) A1460A = 6000 Gates A14V60A = 6000 Gates (3.3V) A14100A = 10000 Gates A14V100A = 10000 Gates (3.3V – ...
Page 4
... Prod uct Plan A1415A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 100-pin Ceramic Pin Grid Array (CPGA) A14V15A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) ...
Page 5
Pro duc t Plan (continued) A14V60A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 208-pin Plastic Quad Flatpack (PQFP) A14100A Device 208-pin Power Quad Flatpack (RQFP) 257-pin Ceramic Pin Grid Array (CPGA) 313-pin Plastic Ball Grid Array ...
Page 6
Hermetic D evice R eso ur ces Device Logic Series Modules Gates A1415 200 1500 A1425 310 2500 A1440 564 4000 A1460 848 6000 A14100 1377 10000 Pin Descrip tion CLKA Clock A (Input) Clock input for clock distribution networks. ...
Page 7
Arch itec ture This section of the data sheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed ...
Page 8
The S-module contains a full implementation of the C-module plus a clearable sequential element that can either implement a latch or flip-flop function. The S-module can therefore implement any function implemented by the C-module. This allows complex combinatorial-sequential functions to ...
Page 9
D ODE MUX Figure 4 • Functional Diagram for I/O Module I/O Pad Drivers All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four signals: OE (Output Enable), IE ...
Page 10
OE SLEW DATAOUT DATAIN IEN INEN OUTEN Figure 5 • Function Diagram for I/O Pad Driver Routed Clocks The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock module (CLKMOD) that selects ...
Page 11
Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two TRACK SEGMENT HF Figure 7 • Horizontal Routing Tracks ...
Page 12
Antifuse Connections An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as ...
Page 13
B1 B0 D01 D00 A1 D10 D11 A0 S-MODULES Figure 9 • Logic Module Routing Interface A cceler ator Se rie s FP GAs – Y+2 Y+2 Y+1 Y+1 Y Y-1 Y-2 LVTs ™ 3 Fami ly B0 ...
Page 14
Operatin g C ondi Abs olute Ma ximum Free air temperature range Symbol Parameter V DC Supply Voltage –0 Input Voltage –0 ...
Page 15
Operating C ond ons A bso lu te Maxi Free air temperature range Symbol Parameter V DC Supply Voltage –0 Input Voltage –0 ...
Page 16
Pa c kag e Th ermal C har The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown ...
Page 17
Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances ...
Page 18
... A1460B 165 A14100A 195 A14V100A 185 A14100B 195 Fixed Clock Loads ( Clock Loads on Device Type dedicated array clock A1415A 104 A14V15A 104 A1425A 160 A14V25A 160 A1440A 288 A14V40A 288 A1440B 288 A1460A 432 A14V60A 432 A1460B 432 ...
Page 19
Timi ng M ode l * Input Delays I/O Module t = 2.8 ns INY t IRD2 0.0 ns INH t = 1.8 ns INSU t = 4.7 ns ICKY ARRAY CLOCK t ...
Page 20
Output B uffe r Del ays GND 50% 50 1.5 V Out 1 DHS, DHS, AC Test Loa ds Load 1 (Used to measure propagation delay) To the output under ...
Page 21
Sequ ential Modu Cha tics Flip-Flops D t SUD CLK Q CLR I /O Mod ule: S eque Inp ut Tim in g Charact ...
Page 22
dule: Sequent put acter is tics D t OUTSU IOCLK PRE, CLR 1-196 D PRE E IOCLK CLR Y (Positive edge triggered) t OUTH ...
Page 23
Pre dictabl nce: Tig htes t Delay ons Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, ...
Page 24
Tim ing D erating Fact per Vol tage) (Commercial Minimum/Maximum Specification) x Tim ing D erating Fact or for D esi ical ...
Page 25
A 1415 A, A 14V15 tic s (Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Internal Array Module PD t Sequential Clock ...
Page 26
A14 A14 V15A har act (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter Description t Input Data Pad to Y INY t Input Reg IOCLK ...
Page 27
A 1415 A, A 14V15 tic s (Worst-Case Commercial Conditions) 1 I/O Module – TTL Output Timing Parameter Description t Data to Pad, High Slew DHS ...
Page 28
A14 A14 V15A har act (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter Description t Input Low to High IOCKH (Pad to I/O Module Input) ...
Page 29
A 1425 A, A 14V25 tic s (Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Internal Array Module PD t Sequential Clock ...
Page 30
A14 A14 V25A har act (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter Description t Input Data Pad to Y INY t Input Reg IOCLK ...
Page 31
A 1425 A, A 14V25 tic s (Worst-Case Commercial Conditions) 1 I/O Module – TTL Output Timing Parameter Description t Data to Pad, High Slew DHS ...
Page 32
A14 A14 V25A har act (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter Description t Input Low to High IOCKH (Pad to I/O Module Input) ...
Page 33
A 1440 A, A 14V40 tic s (Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Internal Array Module PD t Sequential Clock ...
Page 34
A14 A14 V40A har act (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter Description t Input Data Pad to Y INY t Input Reg IOCLK ...
Page 35
A 1440 A, A 14V40 tic s (Worst-Case Commercial Conditions) 1 I/O Module – TTL Output Timing Parameter Description t Data to Pad, High Slew DHS ...
Page 36
A14 A14 V40A har act (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter Description t Input Low to High IOCKH (Pad to I/O Module Input) ...
Page 37
A14 60A , A 14V istic s (Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Internal Array Module PD t Sequential Clock to Q ...
Page 38
A14 A14 V60A har act (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter Description t Input Data Pad to Y INY t Input Reg IOCLK ...
Page 39
A 1460 A, A 14V60 tic s (Worst-Case Commercial Conditions) 1 I/O Module – TTL Output Timing Parameter Description t Data to Pad, High Slew DHS ...
Page 40
A14 A14 V60A har act (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter Description t Input Low to High IOCKH (Pad to I/O Module Input) ...
Page 41
A 1410 14V ris ti cs (Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Internal Array Module PD t ...
Page 42
A14 1 00A , A1 4V100A har (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter Description t Input Data Pad to Y INY t ...
Page 43
A14 100A , teristics (Worst-Case Commercial Conditions 1 I/O Module – TTL Output Timing Parameter Description t Data to Pad, High Slew DHS t ...
Page 44
A14 1 00A , A1 4V100A har (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter Description t Input Low to High IOCKH (Pad to ...
Page 45
Pack age Pin ent s 100-Pin PQFP (Top View ...
Page 46
Pa c kag e Pin Assi gnm 84-Pin PLCC (Top View ...
Page 47
PLCC A1415 Pin Number A14V15 Function 1 VCC 2 GND 3 VCC 4 PRA, I/O 11 DCLK, I/O 12 SDI, I/O 16 MODE 27 GND 28 VCC 40 PRB, I/O 41 VCC 42 GND 43 VCC 45 HCLK, I/O ...
Page 48
Pa c kag e Pin Assi gnm 160-Pin PQFP (Top View ...
Page 49
PQFP A1425 A1440 Pin A14V25 A14V40 Number Function Function 1 GND GND 2 SDI, I/O SDI, I I/O 9 MODE MODE 10 VCC VCC 14 NC I/O 15 GND GND 18 VCC VCC 19 GND GND 20 ...
Page 50
Pa c kag e Pin Assi gnm 208-Pin PQFP, RQFP (Top View ...
Page 51
PQFP, RQFP A1460 A14V60 Pin Number Function 1 GND 2 SDI, I/O 11 MODE 12 VCC 25 VCC 26 GND 27 VCC 28 GND 40 VCC 41 VCC 52 GND VCC PRB, I/O ...
Page 52
Pa c kag e Pin Assi gnm 176-Pin TQFP (Top View ...
Page 53
TQFP A1440 Pin A14V40 Number Function 1 GND 2 SDI, I/O 10 MODE 11 VCC GND 22 VCC 23 GND 32 VCC 33 VCC 44 GND PRB, I/O 65 ...
Page 54
Pa c kag e Pin Assi gnm 100-Pin VQFP (Top View 1-228 ...
Page 55
VQFP A1415 Pin Number A14V15 Function 1 GND 2 SDI, I/O 7 MODE 8 VCC 9 GND 20 VCC PRB, I/O 35 VCC 36 GND 37 VCC 39 HCLK, I/O 50 IOPCL, I/O 51 GND 57 ...
Page 56
Pa c kag e Pin Assi 132-Pin CQFP (Top View) 132 131 130 129 128 127 126 125 124 Pin #1 Index ...
Page 57
CQFP Pin Number A1425 Function GND 3 SDI, I/O 9 MODE 10 GND 11 VCC 22 VCC 26 GND 27 VCC GND 42 GND 43 VCC 48 PRB, I/O 50 HCLK, I/O 58 ...
Page 58
Pa c kag e Pin Assi 196-Pin CQFP (Top View) 196 195 194 193 192 191 190 189 188 Pin #1 Index ...
Page 59
CQFP Pin Number A1460 Function 1 GND 2 SDI, I/O 11 MODE 12 VCC 13 GND 37 GND 38 VCC 39 VCC 51 GND 52 GND 59 VCC 64 GND 77 HCLK, I/O 79 PRB, I/O 86 GND 94 ...
Page 60
Pa c kag e Pin Assi 256-Pin CQFP (Top View) 256 255 254 253 252 251 250 249 248 Pin #1 Index ...
Page 61
CQFP Pin Number A14100 Function 1 GND 2 SDI, I/O 11 MODE 28 VCC 29 GND 30 VCC 31 GND 46 VCC 59 GND 90 PRB, I/O 91 GND 92 VCC 93 GND 94 VCC 96 HCLK, I/O 110 ...
Page 62
Pa c kag e Pin Assi gnm 225-Pin BGA (Top View A1460 Function Location CLKA or I/O C8 CLKB or ...
Page 63
Pack age Pin ent s 313-Pin BGA (Top View ...
Page 64
Pa c kag e Pin Assi gnm 100-Pin CPGA (Top View) A1415 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE PRA OR I/O PRB ...
Page 65
Pack age Pin ent s 133-Pin CPGA (Top View A1425 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK ...
Page 66
Pa c kag e Pin Assi gnm 175-Pin CPGA (Top View A1440 Function CLKA or I/O CLKB or I/O DCLK ...
Page 67
P ackag 207-Pin CPGA (Top View A1460 ...
Page 68
Pa c kag e Pin Assi gnm 257-Pin CPGA (Top View A14100 ...