IP101A ETC-unknow, IP101A Datasheet

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IP101A

Manufacturer Part Number
IP101A
Description
Manufacturer
ETC-unknow
Datasheet

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Features
Copyright © 2004, IC Plus Corp.
10/100Mbps TX
Full-duplex or half-duplex
Supports Auto MDI/MDIX function
Fully compliant with IEEE 802.3/802.3u
Supports IEEE 802.3u auto-negotiation
Supports MII / RMII / SNI interface
IEEE 802.3 full duplex control specification
Supports Automatic Power Saving mode
Supports
compensation
Supports Interrupt function
Supports repeater mode
Single 3.3V power supply with built-in 2.5V
regulator
DSP-based PHY Transceiver technology
Using either 25MHz crystal/oscillator or
50MHz oscillator REF_CLK as clock source
Flexible LED display for speed, duplex, link,
activity and collision
Supports flow control to communicate with
other MAC through MDC and MDIO
0.25u, CMOS technology
48-pin LQFP
Support Lead Free package (Please refer to
the Order Information)
Single port 10/100 Fast Ethernet Transceiver
BaseLine
Wander
(BLW)
1/36
General Description
IP101A LF is an IEEE 802.3/802.3u compliant
single-port Fast Ethernet Transceiver for both
100Mbps and 10Mbps operations. It supports
Auto MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. To improve the system performance, IP101A
LF provides a hardware interrupt pin to indicate
the link, speed and duplex status change. IP101A
LF also provides Media Independent Interface
(MII) / Serial Network Interface (SNI) or Reduced
Media Independent Interface (RMII) to connect
with different types of 10/100Mbps Media Access
Controller (MAC). IP101A LF is designed to use
category
connecting to other LAN devices.
IP101A
advanced CMOS technology, which the chip only
requires 3.3V as power supply and consumes
very low power in the Auto Power Saving mode.
IP101A LF can be implemented as Network
Interface Adapter with RJ-45 for twisted-pair
connection. It can also be easily implemented into
HUB, Switch, Router, Access Point.
LF
5
Transceiver
unshielded
is
twisted-pair
IP101A LF-DS-R12
IP101A LF
fabricated
Data Sheet
Oct 22, 2007
cable
with

Related parts for IP101A

IP101A Summary of contents

Page 1

... To improve the system performance, IP101A LF provides a hardware interrupt pin to indicate (BLW) the link, speed and duplex status change. IP101A LF also provides Media Independent Interface (MII) / Serial Network Interface (SNI) or Reduced Media Independent Interface (RMII) to connect with different types of 10/100Mbps Media Access Controller (MAC) ...

Page 2

... Layout Guideline............................................................................................................................. 30 7 Electrical Characteristics ................................................................................................................ 31 7.1 D.C. Characteristic....................................................................................................... 31 7.1.1 Absolute Maximum Rating...................................................................................... 31 7.1.2 Power Dissipation ................................................................................................... 31 7.1.3 Operating Condition ................................................................................................ 31 7.1.4 Supply Voltage ........................................................................................................ 31 7.2 A.C. Characteristic....................................................................................................... 32 7.2.1 MII Timing ............................................................................................................... 32 7.2.2 RMII Timing............................................................................................................. 33 7.2.3 SMI Timing .............................................................................................................. 34 8 Order Information ........................................................................................................................... 35 9 Package and Mechanical Specification .......................................................................................... 36 Copyright © 2004, IC Plus Corp. 2/36 IP101A LF Data Sheet Oct 22, 2007 IP101A LF-DS-R12 ...

Page 3

... Modify MII reg3 content in page 15. IP101A LF-DS-R08 Remove Circuit diagram. IP101A LF-DS-R09 Modify Pin assignments in page 5. IP101A LF-DS-R10 Delete the “Preliminary” & Modify X1 input Voltage in Page30 IP101A LF-DS-R11 Modify “RXER” Pin description in page 7. IP101A LF-DS-R12 Add SMI timing chart in page 28 & page 34. ...

Page 4

... Clock Recovery 10Mbps 100Mbps Parallel to Serial MLT3/NRZI Decoder 10Mbps 100Mbps NRZ/Manchester DSP Engine Encoder 10Mbps 100Mbps RJ-45 RXI Connector Figure 1: Flow chart of IP101A LF 4/36 IP101A LF Data Sheet RXD 10Mbps Serial to Parallel 10Mbps Manchester/ NRZ Decoder 5B 10Mbps Clock Recovery 10Mbps Squelch 10Mbps Oct 22, 2007 ...

Page 5

... RPTR 41. APS 42. RESET_N 43. ISOL Fast Ethernet Single Phy Transceiver Chip 44. MII_SNIB 45. DGND 46. X1 47. X2 48. INTR Copyright © 2004, IC Plus Corp. IP101A LF 48 pins LQFP package Figure 2 : IP101A LF pins assignment 5/36 IP101A LF Data Sheet 24. RX_ER 23. CRS /LEDMOD 22. RX_DV /CRS_DV 21. RXD0 20. RXD1 19. RXD2 18. RXD3 17 ...

Page 6

... RX_DV pin uses this pin as its reference under MII. O Receive Data: These 4 data lines are transmission path for PHY to send data to MAC and they are synchronizing with RX_CLK. 6/36 IP101A LF Data Sheet Description Internal Pull-Down Internal Pull-Up Power Open Drain Description Oct 22, 2007 IP101A LF-DS-R12 ...

Page 7

... LEDMOD: During power on reset, this pin status is latched to determine at which LED mode to operate, please refer to the LED pins description. (Notice: This pin is pulled down internally) 7/36 IP101A LF Data Sheet Description to avoid the noise interference Oct 22, 2007 IP101A LF-DS-R12 .) ...

Page 8

... Reference Clock: This pin is an input pin operates as 50MHz reference clock (REF_CLK) in RMII mode. O Reference Clock out: This pin could be configured as 50MHz clock output in RMII mode. With 25MHz crystal/oscillator, IP101A LF could generate 50MHz output for RMII mode. I Transmit Enable: For MAC to indicate transmit operation ...

Page 9

... This pin can be directly connected to GND or VCC. (An internal weak pulled-up is used to enable Auto-Negotiation as a default) I Set high to put the IP101A LF into APS mode. This pin can be (PU) directly connected to GND or VCC. Please refer to power down modes description for more information. (An internal weak ...

Page 10

... Label LED and PHY Address Configuration These five pins are latched into the IP101A LF during reset to configure PHY address [4:0] used for MII management register interface. And then, in normal operation after initial reset, they are used as driving pins for status indication LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0] during reset ...

Page 11

... I Transmit Bias Resistor Connection: This pin should be connected to GND via a 6.2K (1%) resistor to define driving current for transmit DAC. 11/36 IP101A LF Data Sheet Oct 22, 2007 IP101A LF-DS-R12 ...

Page 12

... Copyright © 2004, IC Plus Corp. Type Description P Regulator Power Output: This is a regulator power output for IP101A LF digital circuitry. P 3.3V Analog power input: This is a 3.3V power supply for analog circuitry, and it should be decoupled carefully. P Analog Ground: These 2 pins should connect to motherboard’s GND ...

Page 13

... PHY to default state. This bit is self-clearing Software reset 0 = Normal operation 14 Loop-back This bit enables loop-back of transmit data to the receive data path, i.e., TXD to RXD. IP101A LF requires at least 512us to link after programming this bit. TX/RX packets should be activated after 512us enable loop-back 0 = normal operation 13 Speed Selection This bit sets the speed of transmission ...

Page 14

... Reserved 6 MF Preamble The IP101A LF will accept management frames with Suppression preamble suppressed. The IP101A LF accepts management frames without preamble. A Minimum of 32 preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as per IEEE802 ...

Page 15

... Register Descriptions (continued) Bit Name Register 2 : PHY Identifier Register 1 15:0 PHYID1 PHY identifier ID for software recognize IP101A LF Bit Name Register 3 : PHY Identifier Register 2 15:0 PHYID2 PHY identifier ID for software recognize Note : Register 2 and register 3 identifier registers altogether consist of Vender model, model revision number and Organizationally Unique identifier (OUI) information. Total of 32 bits allocate in these 2 registers and they can return all zeroes in all bits if desired. Register 2 contains OUI’ ...

Page 16

... Register Descriptions (continued) Register 4 lists the advertised abilities during auto-negotiation for what will be transmitted to IP101A LF’s Link Partner. Bit Name Register 4 : Auto-Negotiation Advertisement Register 15 NP Next Page bit transmitting the primary capability data page 1 = transmitting the protocol specific data page 14 Reserved ...

Page 17

... Selector Link Partner’s binary encoded node selector Currently only CSMA/CD <00001> is specified Copyright © 2004, IC Plus Corp. Description/Usage 17/36 IP101A LF Data Sheet Default value (h): 0000 <00000>, RO Oct 22, 2007 IP101A LF-DS-R12 ...

Page 18

... LP_NW_ABLE 1 = link partner supports auto-negotiation. Copyright © 2004, IC Plus Corp. Description/Usage It is cleared automatically 18/36 IP101A LF Data Sheet Default value (h): 0000 after the 0, RO Oct 22, 2007 IP101A LF-DS-R12 ...

Page 19

... Set high to bypass the reset DSP mechanism in PCS reset sub-layer 4:3 Reserved 2 Repeater Mode Set high to put IP101A LF into repeater mode 1 APS Mode Set high to enable Auto Power Saving mode 0 Analog Off Set high to power down analog transceiver Copyright © 2004, IC Plus Corp. ...

Page 20

... Flag to indicate link status change interrupt Change 1 Speed Change Flag to indicate speed change interrupt 0 Duplex Change Flag to indicate duplex change interrupt Copyright © 2004, IC Plus Corp. Description/Usage 20/36 IP101A LF Data Sheet Default value (h): 0E00 0, R R/W 1, R/W 1, R/W 1, R Oct 22, 2007 IP101A LF-DS-R12 ...

Page 21

... Functional Description IP101A LF 10/100Mbps Ethernet PHY Transceiver integrates 100 Base-TX and 10 Base-T modules into a single chip. IP101A LF acts as an interface between physical signaling and Media Access Controller (MAC). IP101A LF has several major functions: 1. PCS layer (Physical Coding Sub-Layer): This function contains transmit, receive and carrier sense functional circuitries ...

Page 22

... The transmission pins consists of TXD[3:0], TX_EN and TXC, and at receiving MII pins have RXD[3:0], RXER, RX_DV and RXC. The Management control pins include MDC and MDIO. Copyright © 2004, IC Plus Corp. 22/36 IP101A LF Data Sheet Oct 22, 2007 IP101A LF-DS-R12 ...

Page 23

... Transmitting a packet, MAC will first assert TX_EN and convert the information into 4 bit wide data and then pass the data to IP101A LF. IP101A LF will sample the data according to TX_CLK until TX_EN is low. While receiving a packet, IP101A LF asserts RX_DV high when data present in the medium through RXD[3:0] bus lines ...

Page 24

... Pin 37 (AN_ENA), 38 (DLPX), 39 (SPD) can be configured manually to set IP101A LF’s transmission ability. 1. Enabling Pin 37 (set high) will put IP101A LF to Auto-Negotiation mode, if set low to pin 37, it will put IP101A LF into forced mode. 2. Pin 38 will configure Duplex ability of IP101A LF, at high, IP101A LF is set to Full-Duplex and low will let IP101A LF enter half duplex mode ...

Page 25

... Auto MDIX function IP101A LF will keep sensing incoming signal in MDI RX pair incoming signal is detected, IP101A LF will switch TX and RX pairs automatically trying to establish connection. IP101A LF supports this function both in Auto-Negotiation mode and force mode. LED Configuration IP101A LF provides 2 LED operation modes, ...

Page 26

... SNI, 25MHz crystal or osc from X1,X2 While pin1=1 and pin44=0 has been selected, 50MHz clock will be provided by IP101A LF in RMII mode. We suggest the application circuit as the following : 25M For this configuration, RMII reference clock for IP101A LF is from pin7. Clock skew could be eliminated by adding an external buffer and placing equal trace lengths between buffer outputs and each chip. Copyright © ...

Page 27

... To enter Repeater mode, one can either set pin 40 (RPTR) to high or set 1 to bit 2 of Register 16 will allow IP101A LF to enter Repeater mode. If IP101A LF is used in repeater, CRS will be high process of receiving packets, while IP101A LF is used in a network interface card, CRS will be generated in both transmitting and receiving packets ...

Page 28

... Serial management interface User can access IP101A LF’s MII registers through serial management interface MDC and MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following table. When the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the management entity sends a sequence of 32 contiguous “ ...

Page 29

... Load Capacitance 9 Shunt Capacitance 10 Insulation Resistance 11 Aging Rate A Year Copyright © 2004, IC Plus Corp. Parameter 29/36 IP101A LF Data Sheet Range 25.000 MHz Fundamental Mode +/- 50 ppm +/- 50 ppm -10š ~ +70š 40 ohm Max. 1006W Max Mega ohm Min./DC 100V +/- 5 ppm/year Oct 22, 2007 IP101A LF-DS-R12 ...

Page 30

... Twisted Pair recommendation When routing the TD+/- signal traces from IP101A LF to transformer, the traces should be as short as possible, the termination resistors should be as close as possible to the output of the TD+/- pair of IP101A LF. Center tap of primary winding of these transformers must be connected to analog 2.5V respectively recommended that RD+/- trace pair be route such that the space between it and others is three times space, which can separate individual traces from one another ...

Page 31

... Minimum 3.0 V 0GC Condition Vout=Vcc or GND Vin=Vcc or GND Iout=0mA 31/36 IP101A LF Data Sheet Typical Maximum 3.3V 3.6V 125GC Typical Maximum 3.3V 3.6V 70GC Min Max 0.5*Vcc Vcc+0.5V -0.5V 0.3*Vcc 1.25V 0.42V 0.9*Vcc Vcc 0.1*Vcc 200mA Oct 22, 2007 IP101A LF-DS-R12 ...

Page 32

... Data Sheet Min. Typ. Max. Unit - Min. Typ. Max. Unit - 400 - 0 xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Min. Typ. Max. Unit - 400 - xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Oct 22, 2007 IP101A LF-DS-R12 ...

Page 33

... Figure 4: Clock Timing RMII Notes Initial rising edge of CRS_DV is asynchronous to REFCLK V (max (min (min (max 33/36 IP101A LF Data Sheet Min. Typ. Max. Unit - 40 - Min Typ Max Units - - 3 3 20.0 ² 50 ppm 8.0 10.0 12.0 ns 8.0 10.0 12.0 ns Min Typ Max Units 12.0 15.0 ns 1.0 2.5 ns 1.0 2.5 ns Oct 22, 2007 IP101A LF-DS-R12 us ...

Page 34

... Figure 5: Receive Delay R_RXD Figure 6: RMII Rise and Fall Times Parameter T SU_TXD_RMII Valid Data Figure 7: RMII Transmit Timing Description 34/36 IP101A LF Data Sheet V IH_DIG(MAX) V IL_DIG(MAX) T F_RXD Min Typ Max Units 4 HD_TXD_RMII Min. Typ. Max. Unit Oct 22, 2007 IP101A LF-DS-R12 ...

Page 35

... Part No. IP101A 48-PIN LQFP IP101A LF 48-PIN LQFP Copyright © 2004, IC Plus Corp ite Package Notice - Lead free 35/36 IP101A LF Data Sheet Oct 22, 2007 IP101A LF-DS-R12 ...

Page 36

... FAX : 886-2-2696-2220 Oct 22, 2007 IP101A LF-DS-R12 ...

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