STAC9721T ETC-unknow, STAC9721T Datasheet
STAC9721T
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STAC9721T Summary of contents
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... Pin compatible with the STAC9700/44/45 • SigmaTel Surround (SS3D) Stereo Enhancement ORDERING INFORMATION: PART PACKAGE NUMBER 48-pin TQFP 7mm x7mm x 1.4mm STAC9721T 48-pin TQFP 7mmx7mm x 1.4mm STAC9723T SigmaTel reserves the right to change specifications without notice DATA SHEET STAC9721/23 Stereo AC'97 Codec With Multi-Codec Option • ...
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SigmaTel, Inc. Table of Contents GENERAL DESCRIPTION:.........................1 TABLE OF CONTENTS................................2 TABLE OF CONTENTS – FIGURES ..........3 1. PIN/SIGNAL DESCRIPTIONS .............7 1.1 D I/O IGITAL 1.2 A I/O NALOG 1 /GPIO ILTER EFERENCES 1 OWER AND ...
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SigmaTel, Inc. Table 21. Cold Reset Table 22. Warm Reset Table 23. Clocks Table 24. Data Setup and Hold Table 25. Signal Rise and Fall Times Table 26. AC-Link Low Power Mode Timing Table 27. ATE Test Mode Table 28. ...
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SigmaTel, Inc. Figure 1 . Package Outline SigmaTel 48 pin TQFP PIN Signal Name DVdd1 13 2 XTL_IN 14 3 XTL_OUT 15 4 DVss1 16 5 SDATA_OUT ...
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SigmaTel, Inc. Power Management Digital AC-link Interface SYNC BIT_CLK Registers SDATA_OUT bits SDATA_IN RESET The STAC9721/23 block diagram is illustrated above. It performs fixed 48K sample rate D-A & A-D conversion, mixing, and analog processing. The digital ...
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SigmaTel, Inc. See Appendix A for an alternative connection diagram when using separate supplies. See Appendix B for specific connection requirements prior to operation. 0.1uF 1uF 25 AVdd1 BEEP 13 PHONE 14 AUX_L 15 AUX_R 16 VIDEO_L ...
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SigmaTel, Inc. 1. PIN/SIGNAL DESCRIPTIONS 1.1 Digital I/O These signals connect the STAC9721/23 to its AC'97 controller counterpart, an external crystal, multi- codec selection and external audio amplifier. Signal Name Type RESET # XTL_IN XTL_OUT SYNC BIT_CLK SDATA_OUT SDATA__IN CID0 ...
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SigmaTel, Inc. 1.2 Analog I/O These signals connect the STAC9721/23 to analog sources and sinks, including microphones and speakers. Signal Name Type PC-BEEP I PHONE I MIC1 I MIC2 I LINE-IN-L I LINE-IN-R I CD-L I CD-GND I CD-R I ...
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SigmaTel, Inc. 1.3 Filter/References/GPIO These signals are connected to resistors, capacitors, specific voltages, or provide general purpose I/O. Table 5. Filtering and Voltage References Signal Name Vref Vrefout AFILT1 AFILT2 CAP1 CAP2 CAP3 APOP EAPD 1.4 Power and Ground Signals ...
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SigmaTel, Inc. 2. AC-LINK Below is the figure of the AC-Link point to point serial interconnect between the STAC9721/23 and its companion controller. All digital audio streams and command/status information are communicated over this AC-Link. Please refer to the “Digital ...
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SigmaTel, Inc. 3. DIGITAL INTERFACE 3.1 AC-Link Digital Serial Interface Protocol The STAC9721/23 communicates to the AC'97 controller via a 5-pin digital serial AC-Link interface, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands ...
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SigmaTel, Inc. SYNC OUTGOING STREAMS INCOMING STREAMS TAG PHASE Figure 4. AC'97 Standard Bi-directional Audio Frame 3.1.1 AC-Link Audio Output Frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the ...
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SigmaTel, Inc. SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions stuffed with 0’s by the AC'97 controller. . When mono audio sample streams are sent from the AC'97 controller it is necessary that BOTH ...
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SigmaTel, Inc. If the current command port operation is a read then the entire slot time must be stuffed with 0's by the AC'97 controller. Slot 3: PCM Playback Left Channel 3.1.1.3 Audio output frame slot 3 is the composite ...
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SigmaTel, Inc. Slot 9: PCM Low Frequency Channel 3.1.1.9 Audio output frame slot 9 is the composite digital audio low frequency stream used in a multi-channel application where the STAC9721/23 has been programmed to accept the DAC DAC PCM data ...
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SigmaTel, Inc. corresponding 12 time slots are assigned to input data streams, and that they contain valid data. The following diagram illustrates the time slot based AC-Link protocol. Figure 7 Tag Phase SYNC 12.288 MHz BIT_CLK valid slot1 slot2 SDATA_IN ...
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SigmaTel, Inc. Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by STAC9721/23 during slot 0) ...
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SigmaTel, Inc. 3.2 AC-Link Low Power Mode The STAC9721/23 AC-Link can be placed in the low power mode by programming register 26h to the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low ...
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SigmaTel, Inc. Warm Reset - a warm reset will re-activate the AC-Link without altering the current STAC9721/23 register values. A warm reset is signaled by driving SYNC high for a minimum of 1us in the absence of BIT_CLK. Note: Within ...
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SigmaTel, Inc. Source PC_Beep PHONE MIC1 MIC2 LINE_IN CD VIDEO audio from TV tuner or video camera AUX upgrade synth or other external source PCM out digital audio output from AC'97 Controller LINE_OUT LNLVL_OUT Additional stereo mix of all sources ...
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SigmaTel, Inc. 4.4 Programming Registers: REG NAME D15 D14 D13 D12 D11 D10 D9 # 00h Reset X SE4 SE3 SE2 SE1 SE0 02h Master Volume Mute X 04h LNLVL Volume Mute X 06h Master Volume Mono Mute X 0Ah ...
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SigmaTel, Inc. 4.4.1 Reset Register (Index 00h) Writing any value to this register performs a register reset, which causes all registers to revert to their default values. This register returns the AC’97 ID code of the part when read. 4.4.2 ...
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SigmaTel, Inc. 4.4.4 Analog Mixer Input Gain Registers (Index 0Ch - 18h) These registers control the gain/attenuation for each of the analog inputs. Each step corresponds to approximately 1.5 dB. The MSB of the register is the mute bit. When ...
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SigmaTel, Inc. 4.4.6 Record Gain Registers (Index 1Ch) The 1Ch register adjusts the stereo input record gain. Each step corresponds to 1.5 dB. The 22.5 dB setting corresponds to 0F0Fh. When this bit is set to 1, the level for ...
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SigmaTel, Inc. 4.4.7 3D Control Register (Index 22h) This register is used to control the 3D stereo enhancement function, SigmaTel Surround 3D (SS3D), built into the codec. SS3D provides for a wider soundstage and speaker separation for 2-speaker arrangements. Register ...
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SigmaTel, Inc. External Amplifier Power Down Control 4.4.8.1 The EAPD bit D15 of the Powerdown Control/Status Register (Index 26h) directly controls the output of the EAPD output, pin 45, and produces a logical “1” when this bit is set to ...
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SigmaTel, Inc. 4.4.12 Analog Current Adjust (Index 70h and 72h) The Analog Current Adjust register (index 72h locked register and can only be properly written and read from when ABBAh has been written into register 70h. The BIASx ...
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SigmaTel, Inc. Table 19 External Extended Pins Audio ID CID1, CID0 28h ID1, ID0 CID1 = DVdd floating, CID0 = DVdd or floating CID1 = DVdd floating, CID0 = GND CID1 = GND, 1, ...
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SigmaTel, Inc. values if the software profile of the STAC9721/23 changes the case of silicon level device modifications. operational differences between the existing STAC9721/23 and any future versions. 5. Low Power Modes The STAC9721/23 is capable of operating ...
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SigmaTel, Inc. Figure 12 . STAC9721/23 Powerdown/Powerup flow with analog still alive PR0=1 Normal PR0=0 ADC=1 The above figure illustrates a state when all the mixers should work with the static volume settings that are contained in their associated registers. ...
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SigmaTel, Inc. 6. MULTIPLE CODEC SUPPORT The STAC9721/23 provides support for the multi-codec option according to the Intel AC'97, rev 2.1 specification. By definition there can be only one Primary Codec (Codec ID 00) and up to three Secondary Codecs ...
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SigmaTel, Inc. 6.2 Secondary Codec Register Access Definitions The AC'97 Digital Controller can independently access Primary and Secondary Codec registers by using a 2-bit Codec ID field (chip select) which is defined as the LSBs of Output Slot 0. For ...
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SigmaTel, Inc. 8. EXTENDED CODEC FUNCTIONALITY 8.1 Anti-Pop Circuitry The STAC9721/23 provides an integrated output signal (APOP on pin 34) to aid in low-component-count anti-pop implementations. An audible speaker "pop" can occur when the main power is applied to, or ...
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SigmaTel, Inc. 9.2 Warm Reset Parameter SYNC active high pulse width SYNC inactive to BIT_CLK startup delay 9.3 Clocks BIT_CLK SYNC Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BLT_CLK high pulsewidth (note 1) BIT_CLK low pulse width (note 1) ...
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SigmaTel, Inc. 9.4 Data Setup and Hold (50pF external load) BIT_CLK SDATA_IN SDATA_OUT Parameter Setup to falling edge of BIT_CLK Hold from falling edge of BIT_CLK Note 1: Setup and hold time parameters for SDATA_IN are with respect to the ...
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SigmaTel, Inc. 9.6 AC-Link Low Power Mode Timing Figure 18 SYNC BIT_CLK SDATA_OUT SDATA_IN Table 28 Parameter End of Slot 2 to BIT_CLK, SDATA_IN low 04/07/00 Data Sheet . AC-Link Low Power Mode Timing Slot 1 Slot 2 Data Write ...
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SigmaTel, Inc. 9.7 ATE Test Mode SDATA_IN, BIT_CLK Parameter Setup to trailing edge of RESET# (also applies to SYNC) Setup to trailing edge of RESET# (also applies to SYNC) Rising edge of RESET# to Hi-Z delay Notes: 1. All AC-Link ...
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SigmaTel, Inc. 10. ELECTRICAL SPECIFICATIONS: 10.1 Absolute Maximum Ratings: Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin 10.2 Recommended Operating Conditions PARAMETER Power Supplies Ambient Temperature SigmaTel reserves the right to ...
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SigmaTel, Inc. 10.3 Power Consumption Table 31: Power Consumption at Default Analog Current PARAMETER Digital Supply Current + 5V Digital: DAC and ADC Active + 3.3V Digital: DAC and ADC Active + 3.3V Digital: DAC and ADC Muted Analog Supply ...
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SigmaTel, Inc. Table 33: Reduced Analog Power Settings Typical Supply Current Condition Default Analog Current Reset All Un-Muted ADC, LINE Thru, PC_BEEP active DAC, LINE Thru, PC_BEEP active All but DAC and ADC -25% Analog Current Reset All Un-Muted ADC, ...
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SigmaTel, Inc. 10.4 AC-Link Static Digital Specifications AVss=DVss=0V; 50pF external load) PARAMETER Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-Link inputs) Output Leakage Current (Hi-Z’d ...
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SigmaTel, Inc. 7 Out-of-Band Rejection Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Attenuation, Gain Step Size Input Impedance Input Capacitance Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset ...
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SigmaTel, Inc. 10.6 STAC9723 Analog Performance Characteristics 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz Vrms, 10KΩ/50pF load, Testbench Characterization BW – 20 kHz settings on all gain ...
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SigmaTel, Inc. Vrefout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage Deviation from Linear Phase External Load Impedance Mute Attenuation (0 dB) Notes: 1. With +20 dB Boost on, 1.0Vrms with Boost off 2. ± ...
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SigmaTel, Inc. SPLIT INDEPENDENT POWER SUPPLY OPERATION In PC applications, one power supply input to the STAC9721/23 may be derived from a supply regulator (as shown in Figure 3) and the other directly from the PCI power supply bus. When ...
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SigmaTel, Inc. +5.0V/+3.3V POWER SUPPLY OPERATION NOTES The STAC9721 is capable of operating from a single 5V supply connected to both DVdd and AVdd. Even though the STAC9721 has digital switching levels of 0.2Vdd to 0.5Vdd (See AC Link Electrical ...
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SigmaTel, Inc. 04/07/00 Data Sheet - NOTES - 47 STAC9721 04/07/00 ...
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SigmaTel, Inc. For more information, please contact: 6101 W. Courtyard Dr., Bldg. 1, Suite 100 Tel (512) 343-6636x29, Fax (512) 343-6199 email: sales@sigmatel.com 04/07/00 Data Sheet SigmaTel, Inc. Austin, Texas 78730 http://www.sigmatel.com 48 STAC9721 04/07/00 ...