RTL8305SC ETC-unknow, RTL8305SC Datasheet

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RTL8305SC

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RTL8305SC
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ETC-unknow
Datasheet

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RTL8305SC
SINGLE-CHIP 5-PORT 10/100MBPS SWITCH
CONTROLLER WITH DUAL MII INTERFACES
DataSheet
Rev. 1.2
02 March 2005
Track ID: JATR-1076-21

Related parts for RTL8305SC

RTL8305SC Summary of contents

Page 1

... RTL8305SC SINGLE-CHIP 5-PORT 10/100MBPS SWITCH CONTROLLER WITH DUAL MII INTERFACES DataSheet Rev. 1.2 02 March 2005 Track ID: JATR-1076-21 ...

Page 2

... This document could include technical inaccuracies or typographical errors. USING THIS DOCUMENT This document is intended for use by the software engineer when programming for Realtek RTL8305SC controller chips. Information pertaining to the hardware design of products using these chips is contained in a separate document. ...

Page 3

... Corrected PHY 4 register 18 description, in Table 124, page 81. Add 100Base-TX TD and RD Differential Output Impedance (return loss) columns and delete 10Base-TX TD and RD Differential Output Impedance (return loss) columns, in Section 9.4 AC Characteristics, page 135. 5-port 10/100Mbps Single-Chip Dual MII Switch Controller iii Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 4

... Port 2 Control 2 & VLAN Entry [C] ....................................................................................................................38 6. .....................................................................................................................................................39 ORT EGISTERS 6.4.1. Switch MAC Address ............................................................................................................................................39 6.4.2. Port 3 Control 0....................................................................................................................................................39 6.4.3. Port 3 Control 1....................................................................................................................................................40 6.4.4. Reserved ...............................................................................................................................................................40 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table of Contents ............................................................................................................................................9 P ......................................................................................................................................9 INS P .....................................................................................................................14 NTERFACE INS P ......................................................................................................................16 INS ..............................................................................................................................22 INS P ...................................................................................................................................24 INS iv RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 5

... PHY 1 Register 16~17: Internal Use Register......................................................................................................65 7.2.8. PHY 1 Register 18~19: Internal Use Register......................................................................................................65 7.2.9. PHY 1 Register 22: Port 1 Control Register 0......................................................................................................66 7.2.10. PHY 1 Register 23: Global Option Register 0......................................................................................................66 7.2.11. PHY 1 Register 24: Port 1 Control Register 1 & VLAN ID [B] Membership ......................................................66 5-port 10/100Mbps Single-Chip Dual MII Switch Controller v Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 6

... PHY 4 Register 25: Port 4 Control Register 2 & VLAN ID [E] ...........................................................................83 7.5.13. PHY 4 Register 26: Reserved or VLAN ID [J] Membership ................................................................................83 7.5.14. PHY 4 Register 27: Reserved or VLAN ID [J] .....................................................................................................84 7.5.15. PHY 4 Register 28: Reserved or VLAN ID [O] Membership ...............................................................................84 7.5.16. PHY 4 Register 29: Reserved or VLAN ID [O] ....................................................................................................85 5-port 10/100Mbps Single-Chip Dual MII Switch Controller vi Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 7

... Broadcast Storm Control ....................................................................................................................................126 8.3.14. Broadcast In/Out Drop .......................................................................................................................................126 8.3.15. Loop Detection ...................................................................................................................................................127 8.3.16. MAC Local Loopback Return to External ..........................................................................................................128 8.3.17. Reg.0.14 PHY Digital Loopback Return to Internal...........................................................................................129 5-port 10/100Mbps Single-Chip Dual MII Switch Controller O .....................................................................................................................90 VERVIEW O ..............................................................................................................110 VERVIEW O .......................................................................................................................115 VERVIEW vii RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 8

... A ASE PPLICATION 11. DESIGN AND LAYOUT GUIDE................................................................................................................................145 12. MECHANICAL DIMENSIONS .................................................................................................................................147 12. ECHANICAL IMENSIONS 13. ORDERING INFORMATION....................................................................................................................................148 5-port 10/100Mbps Single-Chip Dual MII Switch Controller ...............................................................................................................................133 ATINGS .........................................................................................................................136 ...................................................................................................................................139 -TX) A .........................................................................................................141 PPLICATION ......................................................................................................................................143 N ..........................................................................................................................148 OTES viii RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 9

... Single-Chip Dual MII Switch Controller List of Tables ............................................................................................................................................. .....................................................................................................................9 IN EFINITIONS P D ...................................................................................................14 IN EFINITIONS P D .....................................................................................................16 IN EFINITIONS ................................................................................................................................22 INS P .....................................................................................................................................24 INS 0 ....................................................................................................................................27 1 ....................................................................................................................................27 2 ....................................................................................................................................28 3 ....................................................................................................................................28 4 ....................................................................................................................................28 5 ....................................................................................................................................29 6 ....................................................................................................................................29 7....................................................................................................................................30 [A] ....................................................................................................................32 NTRY .............................................................................................................................................33 [B] ....................................................................................................................35 NTRY .............................................................................................................................................36 [C] ....................................................................................................................38 NTRY ..............................................................................................................................................39 [D] ....................................................................................................................40 NTRY .............................................................................................................................................41 [E].....................................................................................................................43 NTRY .............................................................................................................................................44 ix RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

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... EGISTER O R 1...................................................................................................71 LOBAL PTION EGISTER & VLAN ID [C] M ONTROL EGISTER & VLAN ID [C] ......................................................................72 ONTROL EGISTER R ...............................................................................................................72 ESERVED EGISTER ...................................................................................................72 EMBERSHIP R ...............................................................................................................73 ESERVED EGISTER R ...............................................................................................................73 ESERVED EGISTER x RTL8305SC ..............................................................................56 .................................................61 EMBERSHIP ..................................................66 EMBERSHIP [B]..................................................................67 NTRY ................................................71 EMBERSHIP Track ID: JATR-1076-21 Rev. 1.2 Datasheet ...

Page 11

... DENTIFIER 2 .....................................................................................................................87 DENTIFIER -N A EGOTIATION DVERTISEMENT .............................................................................................................................................89 .............................................................................................................................................89 PHY 4 PHY 5.................................................................................................103 AND ..................................................................................................................................112 ......................................................................................................................................119 F .......................................................................................................................124 ORMAT .............................................................................................................................125 DDRESS / ..........................................................................................................130 CT RUTH ABLE T 2SB1188................................................................................................132 RANSISTOR /R ...............................................................................................................133 ATINGS ...........................................................................................................................................137 ...........................................................................................................................................139 C .......................................................................................................................140 ONDITIONS ........................................................................................................................................141 .........................................................................................................................................148 xi ................................................76 EMBERSHIP ................................................82 EMBERSHIP ......................................................................................88 Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 12

... RANSCEIVER PPLICATION xii -T UTP NTERFACES PPLICATION - ODE NTERFACES PPLICATION -T UTP NTERFACES PPLICATION -T UTP NTERFACES PPLICATION A VLAN D ...........................122 AG WARE IS ISABLED ..................................................................................131 T ................................................................141 AP T ....................................................................142 AP Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet C ............101 IRCUIT C .......101 IRCUIT C .............102 IRCUIT C .............102 IRCUIT ...

Page 13

... UTP ports and needs no SD+/- pins, a development using Realtek proprietary technology. To compensate for the lack of auto-negotiation in 100Base-FX applications, the RTL8305SC can be forced into 100Base-FX half or full duplex mode, and can enable or disable flow control in fiber mode. ...

Page 14

... In router applications, the router may want to know which input port this packet came from. The RTL8305SC supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress. Using this function, VID information carried in the VLAN tag will be changed to PVID. The RTL8305SC also provides an option to admit VLAN tagged packets with a specific PVID only ...

Page 15

... A power saving mode is implemented on a per-port basis. Each port automatically enters power saving mode 10 seconds after the cable is disconnected from it. The RTL8305SC also implements a power down mode on a per-port basis. Users can set MII Reg.0.11 to force the corresponding port to enter power down mode, which disables all transmit/receive functions, except SMI (MDC/MDIO management interface) ...

Page 16

... ARP VLAN for broadcast packets Leaky VLAN for unicast packets VLAN tag Insert/Remove function Supports QoS function on each port: QoS based on: (1) Port-based, (2) VLAN tag, (3) TCP/IP header’s TOS/DS Supports two-level priority queues Weighted round robin service 4 Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 17

... Physical layer port Polarity Detection and Correction function Optional EEPROM interface for configuration 25MHz crystal or 3.3V OSC input Single 3.3V power input can be transformed to 1.8V via a low-cost external BJT transistor Low power, 1.8/3.3V, 0.18µm CMOS technology, 128-pin PQFP package 5 Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 18

... MAC3 Engine3 Switch MAC4 Engine4 PHY Mode MII Mode LED Select Control MAC Circuit Mode MII PHY Mode MII/SNI Figure 1. Block Diagram 6 RTL8305SC Datasheet Lookup Table Packet Buffer DISBRDCTRL ENBKPRS RESET# X1 Global X2 Function CK25MOUT SEL_MIIMAC EN_RST_BLNK LED_BLNK_TIME LED_SPD[4:0] LED_ACT[4:0] LED_DUP[4:0] LED_ADD[4:0] ...

Page 19

... Note: When DISDUALMII=1, the function of pins 83~86 and pin 88 follows the names before the parenthesis ‘( )’. When DISDUALMII=0, pin names in parenthesis ‘( )’ will become functional and original pin functions will not apply. 5-port 10/100Mbps Single-Chip Dual MII Switch Controller RTL8305SC Figure 2. Pin Assignments 7 RTL8305SC Datasheet 64 DGND 63 MRXD[1]/PTXD[1] 62 DVDD33 ...

Page 20

... PU 55 I/O AVDD18 I/O AGND PD 59 I/O VCTRL DTEST2 DTEST1 PU 62 DVDD AGND 63 I IBREF PU 64 DGND AVDD18 8 RTL8305SC Datasheet Pin No. Type I DVDD I I ...

Page 21

... When enabled, the MAC circuit of port 4 can be set as MAC mode MII, PHY mode MII, or PHY mode SNI. The PHY circuit of port 4 is set as PHY mode MII. The PHY circuit of port 4 can optionally be set as UTP or fiber mode according to the P4MOD[1:0] configuration. 9 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 22

... Regardless of whether DISDUALMII=1 or=0, this pin provides the link status to the Port 4 MAC part in PHY 5 MII register 1.2 when the Port 4 MAC part is configured in MAC mode MII/PHY mode MII/PHY mode SNI. 10 RTL8305SC Datasheet 10: 100Base-FX mode 00: PHY mode SNI 00: PHY mode SNI Track ID: JATR-1076-21 Rev. 1.2 ...

Page 23

... This pin straps the initial duplex status of Port 4 upon reset. P4MODE[1:0]=00 (PHY mode SNI) This pin straps the initial duplex status of Port 4 upon reset. In MAC mode MII/PHY mode MII/PHY mode SNI, the configuration of this pin will set the duplex status of the internal register upon reset. 11 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 24

... This pin straps the initial speed status of Port 4 upon reset. P4MODE[1:0]=00 (PHY mode SNI) The speed is dedicated to 10MHz. This pin should be pulled down. In order to provide 100M as the default value for PHY, this pin is set as high active. 12 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 25

... This pin straps the initial flow control status of Port 4 upon reset. P4MODE[1:0]=00 (PHY mode SNI) Flow control should be disabled. This pin must be pulled down. In order to enable flow control ability for the PHY, this pin is set as high active. 13 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 26

... Pin Name Pin No. SEL_MIIMAC#/ 68 DisDSPri /(P4PHY_ MODE) 5.3. Port 4 MAC Circuit Interface Pins The external device must be 3.3V compatible since the digital output of the RTL8305SC is 3.3V. Table 4. Port 4 MAC Circuit Interface Pin Definitions Pin Name Pin No. MRXD[3:0]/ 61, 63, 66, 67 PTXD[3:0] MRXDV/PTXEN 60 MRXC/PTXC 59 5-port 10/100Mbps Single-Chip Dual MII Switch Controller ...

Page 27

... Bi-color Link/Act in Bi-color LED mode, whose polarity depends on Spd status. Link/Act/Spd: Link, Activity, and Speed Indicator. ON for link established. Blinking every 43ms when the corresponding port is transmitting or receiving at 100Mbps. Blinking every 120ms when the port is transmitting or receiving at 10Mbps. 15 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 28

... Pin Name Pin No. MTXEN/PRXDV 52 /Internal MTXC/PRXC 51 5.4. Port 4 PHY Circuit Interface Pins The external device must be 3.3V compatible as the digital output of the RTL8305SC is 3.3V. Table 5. Port 4 PHY Circuit Interface Pin Definitions Pin Name Pin No. DISPORTPRI[4] 88 (PHY2PTXD[3]) DISPORTPRI[3] 86 (PHY2PTXD[2]) DISPORTPRI[2] 85 (PHY2PTXD[1]) 5-port 10/100Mbps Single-Chip Dual MII Switch Controller ...

Page 29

... For PHY mode MII, this is transmit/receive data clock, PTXC/PRXC (acts as output). Input Upon Reset: Weighted round robin ratio of priority queue. The frame service rate of High-priority queue: Low-priority queue QWEIGHT[1:0]=11: 16:1 QWEIGHT[1:0]=10: Always high priority queue first QWEIGHT[1:0]=01: 8:1 QWEIGHT[1:0]=00: 4:1 Power on strapping is independent of DISDUALMII configuration. 17 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 30

... Force Half Back Pressure ability of Force mode (UTP Force mode or FX mode)’ Strap after reset for initial value of Group X ‘UTP NWAY Full’, or ‘UTP Force Full or Half mode’, or ‘FX Full or Half mode’. Power on strapping is independent of DISDUALMII configuration. 18 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 31

... I Active low reset signal To complete the reset function, this pin must be asserted for at least 1ms. After reset, about 30ms is needed for the RTL8305SC to complete internal test functions and initialization. This pin is a Schmitt input. 19 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev ...

Page 32

... Output After Reset = Used for 2 PU LEDMode[1:0]=11 -> Link/Act: (On=Link, Off=No Link, Flash= activity) LEDMode[1:0]=10 -> Act: (Off=No activity, On= activity) LEDMode[1:0]=01 -> RxAct: (Off=No activity, On=Rx activity) LEDMode[1:0]=00 -> Reserved Input Upon Reset = Refer to Table 9, on page 22, and Table 10, on page 24. 20 RTL8305SC Datasheet st LED. nd LED. Track ID: JATR-1076-21 Rev. 1.2 ...

Page 33

... If Input=1: Output 0=Network loop is detected. 1=No loop. => If Input=0: Output 1=Network loop is detected. 0=No loop. Input Upon Reset = Enable defer 1: Enable Carrier Sense Deferring function for half duplex back pressure. 0: Disable Carrier Sense Deferring function for half duplex back pressure. 21 RTL8305SC Datasheet rd LED. th LED. Track ID: JATR-1076-21 Rev. 1.2 ...

Page 34

... Serial EEPROM and SMI Pins As the output of the RTL8305SC is 3.3V, the serial EEPROM and external device must be 3.3V compatible. Pin Name Pin No. Type SCL_MDC 74 I/O PU SDA_MDIO 75 I/O PU 5.8. Strapping Pins Pins that are dual function pins are outputs for LED or inputs for strapping. Below are strapping descriptions only ...

Page 35

... Input Upon Reset = Broadcast Input Drop PU 1: Use Broadcast Input drop mechanism 0: Use Broadcast Output drop mechanism Output After Reset = Used for LED. I/O 4 Input Upon Reset = Maximum Frame Length PU 1: 1536 Bytes 0: 1552 Bytes Output After Reset = Used for LED. 23 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 36

... PU 1: Enable auto-negotiation (NWAY mode) 0: Disable auto-negotiation (Force mode) Upon reset, this pin sets Reg.0.12 of Group Y. Strap after reset for initial value of UTP mode only. This pin is not used for FX. Output After Reset = Used for LED. 24 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 37

... Upon reset, this pin sets the default value of Reg.0.8. On reset, this pin also sets NWay full-duplex ability on Reg.4.8 and Reg.4.6. Strap after reset for initial value of Group Y UTP or FX mode. FX can be Force 100 Full or Force 100 Half. Output After Reset = Used for LED. 25 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 38

... DVDD18 43, 53, 70, 100 DVDD33 62, 87, 106 DGND 39, 50, 64, 79, 94, 102, 112 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 11. Power Pins Type Drive (mA) Description P 1.8V Analog Power P 3.3V Analog Power P Analog Ground P 1.8V Digital Power P 3.3V Digital Power P Digital Ground 26 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 39

... Disable 802.1Q tagged-VID Aware function. The RTL8305SC will not check the tagged VID on received frames to perform tagged-VID VLAN mapping. Under this configuration, the RTL8305SC only uses the per port VLAN index register to perform Port-Based VLAN mapping 0: Enable the Member Set Filtering function of VLAN Ingress Rule. The ...

Page 40

... On 43ms, then Off 43ms 0: On 120ms, then Off 120ms The frame service ratio between the high priority queue and low priority queue is: 11=16:1 10=Always high priority queue first 01=8:1 00=4:1 1: Disable Broadcast Storm Control 0: Enable Broadcast Storm Control 28 RTL8305SC Datasheet Default 1 1 Default 1111 Default 0 ...

Page 41

... Enable VLAN. The default VLAN membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual VLANs. This default membership configuration may be modified by setup internal registers via the SMI interface or EEPROM Table 18. Global Control Register6 Description 29 RTL8305SC Datasheet Default 1 1 Default 1 ...

Page 42

... Description For port 0 egress packets 11=Do not insert or remove VLAN tags to/from packet 10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets 00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets 30 RTL8305SC Datasheet Default Default ...

Page 43

... Disable Diffserv priority classification for ingress packets on port 0 0: Enable Diffserv priority classification 1: Disable port based priority QoS function on port 0 0: Enable port based priority QoS function on port 0. Ingress packets on port 0 will be classed as high priority Table 22. Port 0 Control 2 Description Table 23. Port 0 Control 3 Description 31 RTL8305SC Datasheet Default ...

Page 44

... VLAN Entry [A] This register along with byte 15.3~15.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A Port 0 Control 4 & VLAN Entry [A] This register along with byte 14.7~14.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A 32 RTL8305SC Datasheet Default 0001 0000 ...

Page 45

... For port 1 egress packets 11=Do not insert or remove VLAN tags to/from packet 10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets 00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets 33 RTL8305SC Datasheet Default 0xFF 0xFF 0xFF 0xFF ...

Page 46

... Reserved 26.3~ 26.0 6.2.5. Port 1 Control 3 Name Byte.bit Reserved 27.7 Internal Use 27.6 Reserved 27.5~ 27.0 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 27. Port 1 Control 1 Table 28. Port 1 Control 2 Description Table 29. Port 1 Control 2 Description 34 RTL8305SC Datasheet Default Default 1111 Default 1111 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 47

... This register, along with byte 30.7~30.0, defines the IEEE 802.1Q 12-bit VLAN [11:8] identifier of VLAN B. 31.0 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 30. Port 1 Control 4 & VLAN Entry [B] VLAN Entry [B] Port 1 Control 4 VLAN Entry [B] Port 1 Control 4 & VLAN Entry [B] 35 RTL8305SC Datasheet Default 0010 0001 ...

Page 48

... For port 2 egress packets 11=Do not insert or remove VLAN tags to/from packet 10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets 00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets 36 RTL8305SC Datasheet Default 0xFF 0xFF 0xFF 0xFF ...

Page 49

... Disable Diffserv priority classification for ingress packets on port 2 0: Enable Diffserv priority classification 1: Disable port based priority QoS function on port 2 0: Enable port based priority QoS function on port 2. Ingress packets on port 2 will be classed as high priority Table 34. Reserved Description 37 RTL8305SC Datasheet Default ...

Page 50

... This register along with byte 46.7~46.0 defines the IEEE 802.1Q 12-bit VLAN [11:8] 0 identifier of VLAN C 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 35. Port 2 Control 2 & VLAN Entry [C] VLAN Entry [C] Port 2 Control 2 VLAN Entry [C] Port 2 Control 2 & VLAN Entry [C] 38 RTL8305SC Datasheet Default 0100 0010 ...

Page 51

... For port 3 egress packets 11=Do not insert or remove VLAN tags to/from packet 10=Insert VLAN tags to non-tagged packets 01=Remove tag from tagged packets 00=Replace the VLAN tags for tagged packets and insert a VLAN tag to non-tagged packets 39 RTL8305SC Datasheet Default 0x52 0x54 0x4C 0x83 ...

Page 52

... Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN D 10010 means port 4 and 1 are the members of VLAN D 11111 means all 5 ports are the members of VLAN D 40 RTL8305SC Datasheet Default ...

Page 53

... This register along with byte 61.3~61.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D Port 3 Control 2 & VLAN Entry [D] This register along with byte 60.7~60.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D Table 41. Internal Use Register Description 41 RTL8305SC Datasheet 0011 0000 ...

Page 54

... Enable 802.1p priority classification on port 4 1: Disable Diffserv priority classification for ingress packets on port 4 0: Enable Diffserv priority classification 1: Disable port based priority QoS function on port 4 0: Enable port based priority QoS function on port 4. Ingress packet on port 4 will be classified as high priority 42 RTL8305SC Datasheet Default ...

Page 55

... Reg.24.[4:0] and VLAN ID [E] in PHY4 Reg.25.[11:0]. VLAN Entry [E] This register, along with byte 75.3~75.0, defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E Port 4 Control 2 & VLAN Entry [E] This register, along with byte 74.7~74.0, defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E 43 RTL8305SC Datasheet Default 0x00 0x00 Default 1 1 ...

Page 56

... E.g.: 10001 means port 4 and 0 are the members of VLAN F 10010 means port 4 and 1 are the members of VLAN F 11111 means all 5 ports are the members of VLAN F VLAN identifier of VLAN F VLAN identifier of VLAN F 44 RTL8305SC Datasheet Default 0 100 0 000 Default 100 ...

Page 57

... VLAN G 10010 means port 4 and 1 are the members of VLAN G 11111 means all 5 ports are the members of VLAN G VLAN identifier of VLAN G VLAN identifier of VLAN G Table 50. VLAN Entry [H] VLAN Entry [H] 45 RTL8305SC Datasheet Default 000 1 0010 0110 0000 0000 ...

Page 58

... This register along with byte 96.7~96.0 defines the IEEE 802.1Q 12-bit VLAN [11:8] identifier of VLAN J 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 51. VLAN Entry [I] VLAN Entry [I] Table 52. VLAN Entry [J] VLAN Entry [I] 46 RTL8305SC Datasheet Default 000 1 1000 1000 0000 0000 1000 1111 ...

Page 59

... E.g.: 10001 means port 4 and 0 are the members of VLAN L 10010 means port 4 and 1 are the members of VLAN L 11111 means all 5 ports are members of VLAN L VLAN identifier of VLAN L VLAN identifier of VLAN L 47 RTL8305SC Datasheet Default 000 1 0001 1010 0000 0000 ...

Page 60

... VLAN N This register along with byte 113.3~113.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN N This register along with byte 112.7~112.0 defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN M 48 RTL8305SC Datasheet Default 000 1 0100 1100 ...

Page 61

... E.g.: 10001 means port 4 and 0 are the members of VLAN P 10010 means port 4 and 1 are the members of VLAN P 11111 means all 5 ports are members of VLAN P VLAN identifier of VLAN P VLAN identifier of VLAN P 49 RTL8305SC Datasheet Default 000 1 1111 1110 0000 0000 ...

Page 62

... VLAN ID [K] Membership 0 29 Reserved 1 29 VLAN ID [ Reserved 1 30 VLAN ID [P] Membership 0 31 Reserved 1 31 VLAN ID [ Control Register 1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 50 RTL8305SC Datasheet Latch High until clear Self Clearing Track ID: JATR-1076-21 Rev. 1.2 ...

Page 63

... VLAN ID [ Reserved 1 28 VLAN ID [M] Membership 0 29 Reserved 1 29 VLAN ID [ Control Register 1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 5 Auto-Negotiation Link Partner Ability Register 6 Auto-Negotiation Expansion Register 51 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 64

... Reserved 1 26 VLAN ID [J] Membership 0 27 Reserved 1 27 VLAN ID [ Reserved 1 28 VLAN ID [O] Membership 0 29 Reserved 1 29 VLAN ID [ Control Register 1 Status Register 2 PHY Identifier 1 3 PHY Identifier 2 4 Auto-Negotiation Advertisement Register 52 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 65

... This bit can be set through SMI (Read/Write). When 100FX mode is enabled, this bit=0 (Read only). 100FX must be in Force Mode. In order to avoid errors, the RTL8305SC will ignore the action of this bit when writing Reg0. 100FX mode Power down. All functions will be disabled except SMI ...

Page 66

... Not 10Base-TX half duplex capable RO RO The RTL8305SC will accept management frames with preamble suppressed. (The RTL8305SC accepts management frames without preamble. Minimum preamble of 32 bits is required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as defined in IEEE 802 ...

Page 67

... Name 3.[15:10] OUI 3.[9:4] Model Number 3.[3:0] Revision Number 7.1.5. PHY 0 Register 4 for Port 0: Auto-Negotiation Advertisement Note: Each time the link ability of the RTL8305SC is reconfigured, the auto-negotiation process should be executed to allow the configuration to take effect. Table 64. PHY 0 Register 4: Auto-Negotiation Advertisement Reg.bit Name 4.15 Next Page 4.14 Acknowledge 4 ...

Page 68

... When auto negotiation is disabled, this bit will be set if Reg0.13=0 and Reg0.8=0 after link is established. RO [00001]=IEEE 802.3 Table 66. PHY 0 Register 16: Global Control 0 Mode Description RW 1: Select the registers in page 1 0: Select the registers in page 0 56 RTL8305SC Datasheet Default ...

Page 69

... RW 1: Soft reset. This bit is self-clearing SC If this bit is set to 1, the RTL8305SC will reset all internal registers except PHY registers, and will not load configurations from EEPROM or strapping pins. Software reset is designed to provide a convenient way for users to change the configuration via SMI ...

Page 70

... Disable VLAN 0: Enable VLAN. The default VLAN membership configuration by internal register is port 4 overlapped with all the other ports, to form 4 individual VLANs. This default membership configuration may be modified by setting up internal registers via the SMI interface or EEPROM RW 58 RTL8305SC Datasheet Default 1111 0 0 ...

Page 71

... Disable dual MII interface of port 4. Only provides MII interface for the MAC circuit of port 4 0: Enable dual MII interface of port 4. Provides MII interface for the MAC circuit of port 4, and also provides MII interface for the PHY circuit of port 4 59 RTL8305SC Datasheet Default Pin EnDefer strap option Default=1 ...

Page 72

... VLAN tags from packets then add new tags to them. The inserted tag is the ingress port’s ‘Default tag’, which is indexed by port 0’s ‘Port based VLAN index’. This is a replacement processing for tagged packets and an insertion for untagged packets 60 RTL8305SC Datasheet Default ...

Page 73

... VLAN A 10010 means port 4 and 1 are the members of VLAN A 11111 means all 5 ports are the members of VLAN A Mode Description Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A 61 RTL8305SC Datasheet Default 0000 ...

Page 74

... VLAN F Table 75. PHY 0 Register 27: Reserved Register Mode Description Table 76. PHY 0 Register 27: VLAN ID [F] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN F 62 RTL8305SC Datasheet Default 0x5105 Default 1111 1111 111 1 0001 Default ...

Page 75

... VLAN K Table 79. PHY 0 Register 29: Reserved Register Mode Description Table 80. PHY 0 Register 29: VLAN ID [K] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN K 63 RTL8305SC Datasheet Default 0x0020 Default 1111 1111 111 1 0001 Default ...

Page 76

... VLAN P Table 83. PHY 0 Register 31: Reserved Register Mode Description Table 84. PHY 0 Register 31: VLAN ID [P] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN P 64 RTL8305SC Datasheet Default Default 1111 1111 111 1 0001 Default Default ...

Page 77

... PHY 1 Register 18~19: Internal Use Register Table 86. PHY 1 Register 18~19: Internal Use Register Reg.bit Name 18 Internal Use 19 Internal Use 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Mode Description RW RW Mode Description RTL8305SC Datasheet Default 0xFFFF 0xFFFF Default 0xFFFF 0xFFFF Track ID: JATR-1076-21 Rev. 1.2 ...

Page 78

... VID is not the same as the PVID. The default value of this register is 0001, which indexes to the VLAN entry [B] that is composed of VLAN ID [B] Membership Bit [4:0] in PHY1 Reg.24.[4:0] and VLAN ID [B] in PHY1 Reg.25.[11:0 RTL8305SC Datasheet Default 1111 1111 Default 0001 ...

Page 79

... VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for Port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN G 10010 means port 4 and 1 are the members of VLAN G 11111 means all 5 ports are members of VLAN G 67 RTL8305SC Datasheet Default 1 0010 Default 1 1 ...

Page 80

... Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN L 10010 means port 4 and 1 are the members of VLAN L 11111 means all 5 ports are members of VLAN L 68 RTL8305SC Datasheet Default 0x1F10 Default 1111 0000 0000 ...

Page 81

... Single-Chip Dual MII Switch Controller Table 96. PHY 1 Register 29: Reserved Register Mode Description Table 97. PHY 1 Register 29: VLAN ID [L] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN L 69 RTL8305SC Datasheet Default 0x02C5 Default 1111 0000 0000 1011 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 82

... PHY 2 Register 18~19: Internal Use Register Table 99. PHY 2 Register 18~19: Internal Use Register Reg.bit Name 18 Internal Use 19 Internal Use 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Mode Description RW RW Mode Description RTL8305SC Datasheet Default 0xFFFF 0xFFFF Default 0xFFFF 0xFFFF Track ID: JATR-1076-21 Rev. 1.2 ...

Page 83

... VID is not the same as the PVID. The default value of this register is 0010, which indexes to the VLAN entry [C] that is composed of VLAN ID [C] Membership Bit [4:0] in PHY2 Reg.24.[4:0], and VLAN ID [C] in PHY2 Reg.25.[11:0 RTL8305SC Datasheet Default 0000 0010 0000 Default 0010 1 1 ...

Page 84

... VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN H 10010 means port 4 and 1 are the members of VLAN H 11111 means all 5 ports are the members of VLAN H 72 RTL8305SC Datasheet Default 1 0100 Default 1 1 ...

Page 85

... Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN M 10010 means port 4 and 1 are the members of VLAN M 11111 means all 5 ports are the members of VLAN M 73 RTL8305SC Datasheet Default 0xA9CD Default 1111 0000 0000 ...

Page 86

... Reserved ] 29.[11:0] VLAN ID [M] 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Mode Description Table 110. PHY 2 Register 29: VLAN ID [M] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN M. 74 RTL8305SC Datasheet Default 0xB01F Default 1111 0000 0000 1100 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 87

... Single-Chip Dual MII Switch Controller Mode Description RW 16.[15:8] = Switch MAC Address Byte 4 16.[7:0] = Switch MAC Address Byte 5 RW 17.[15:8] = Switch MAC Address Byte 2 17.[7:0] = Switch MAC Address Byte 3 RW 18.[15:8] = Switch MAC Address Byte 0 18.[7:0] = Switch MAC Address Byte 1 75 RTL8305SC Datasheet Default 0x5452 0x834C 0xC005 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 88

... VID is not the same as the PVID. The default value of this register is 0011, which indexes to the VLAN entry [D] that is composed of VLAN ID [D] Membership Bit [4:0] in PHY3 Reg.24.[4:0], and VLAN ID [D] in PHY3 Reg.25.[11:0 RTL8305SC Datasheet Default 0x0000 0x0000 0x0000 Default 0011 ...

Page 89

... VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN I 10010 means port 4 and 1 are the members of VLAN I 11111 means all 5 ports are the members of VLAN I 77 RTL8305SC Datasheet Default 1 1000 Default 1 1 ...

Page 90

... Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN N 10010 means port 4 and 1 are the members of VLAN N 11111 means all 5 ports are the members of VLAN N 78 RTL8305SC Datasheet Default 0xA464 Default 1111 0000 0000 ...

Page 91

... Reserved 29.[15:12 ] 29.[11:0] VLAN ID [N] 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Mode Description Table 122. PHY 3 Register 29: VLAN ID [N] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN N. 79 RTL8305SC Datasheet Default 0x2154 Default 1111 0000 0000 1101 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 92

... Reserved 16.1 Command execution 16.0 Read or write operation 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Mode Description RW 1: Trigger a command to read or write lookup table 0: Indicate this command is done RW 1: Read cycle 0: Write cycle 80 RTL8305SC Datasheet Default 0000 0000 0000 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 93

... Indirect Data 3 [15:8] = Source MAC Address [39:32] (Byte 0) Mode Description RW Classifies priority for incoming IEEE 802.1Q packets, if IEEE 802.1p priority classification is enabled. ‘User priority’ is compared against this value. >=: Classify as high priority <: Classify as low priority RTL8305SC Datasheet Default 0x00 0x00 0x00 0x00 Default 100 0 0000 0 100 ...

Page 94

... VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN E 10010 means port 4 and 1 are the members of VLAN E 11111 means all 5 ports are the members of VLAN E 82 RTL8305SC Datasheet Default 0100 ...

Page 95

... VLAN will be broadcast to the ports specified in this field. Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN J 10010 means port 4 and 1 are the members of VLAN J 11111 means all 5 ports are the members of VLAN J 83 RTL8305SC Datasheet Default ...

Page 96

... Bit 0 stands for port 0, bit 4 stands for port 4. E.g.: 10001 means port 4 and 0 are the members of VLAN O 10010 means port 4 and 1 are the members of VLAN O 11111 means all 5 ports are the members of VLAN O 84 RTL8305SC Datasheet Default Default 1111 0000 0000 ...

Page 97

... Name Reserved 29.[15:12 ] 29.[11:0] VLAN ID [O] 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Mode Description Table 135. PHY 4 Register 29: VLAN ID [O] Mode Description RW Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN O 85 RTL8305SC Datasheet Default Default 1111 0000 0000 1110 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 98

... Normal operation (permanently= Full duplex operation 0: Half duplex operation When NWay is enabled, this bit reflects the result of auto- negotiation (Read only). When NWay is disabled, this bit may be set through SMI (Read/Write). 86 RTL8305SC Datasheet Default 0 0 Pin P4SPDSTA strap option Pin P4ANEG ...

Page 99

... RO 1: 10Base-TX full duplex capable (permanently= 10Base-TX half duplex capable (permanently= The RTL8305SC will accept management frames with preamble suppressed (permanently= Auto-negotiation process completed. MII Reg.4, 5 are valid if this bit is set (permanently= remote fault (permanently=0) ...

Page 100

... Single-Chip Dual MII Switch Controller Mode Description RO 1: Next Page enabled 0: Next Page disabled (Permanently=0) RO Permanently= Advertises that the RTL8305SC has detected a remote fault 0: No remote fault detected Advertises that the RTL8305SC possesses 802.3x flow control capability 0: No flow control capability RO ...

Page 101

... If PHY 5 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=0, Reg4.5=1, the RTL8305SC will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=0 If the CPU polls register 5, the RTL8305SC replies with the contents in register 4 If the CPU polls register 4, the RTL8305SC replies with the contents in register 4 7 ...

Page 102

... GroupY = Ports 2 and 3). The GxMode/GyMode/P4Mode[1:0] pins are used to select the operation mode (UTP/FX for GroupX and GroupY, UTP/FX/PHY mode MII/PHY mode SNI/MAC mode MII for Port 4). Upon reset, in addition to using strapping pins, the RTL8305SC can be configured with an EEPROM or read/write operation by a CPU via the MDC/MDIO interface. ...

Page 103

... MAC mode and output for PHY mode. Refer to Figure 3, page 93 to check the relationship between the RTL8305SC and the external device. Tip: Connect the input of the RTL8305SC to the output of the external device. The RTL8305SC has no RXER, TXER, and CRS pins for MII signaling. Because the RTL8305SC does not support pin CRS necessary to connect the MTXEN/PRXDV (output) of PHY mode to both CRS and RXDV (input) of the external device ...

Page 104

... MRXC runs at 2.5MHz. In SNI (serial) mode (P4MODE[0]=0), P4SPDSTA has no effect and should be pulled-down. SNI mode operates at 10Mbps only, with MTXC and MRXC running at 10MHz. In SNI mode the RTL8305SC does not loopback an RXDV signal as a response to TXEN, and does not support the heartbeat function (asserting COL signal for each complete TXEN signal) ...

Page 105

... PHY Mode MII 51-MTXC/PRXC 52-MTXEN/PRXDV 54-MTXD[0]/PRXD[0] 59-MRXC/PTXC 60-MRXDV/PTXEN 61-MRXD[0]/PTXD[0] 58-MCOL/PCOL PHY Mode SNI Figure 3. Port 4 Operating Mode Overview 93 RTL8305SC Datasheet RXC CRS RXDV VDSL/ 4 RXD[3:0] HomePNA/ TXC Single PHY TXEN 4 TXD COL 25MHz ...

Page 106

... MAC Mode MII In HomePNA or other PHY applications, the RTL8305SC provides the MII interface to the underlying HomePNA or other physical device in order to communicate with other types of LAN media. In such applications, the P4MODE[1:0] pins are floating upon reset and the RTL8305SC supports the UTP/MII auto-detection function ...

Page 107

... SMI on a per-port basis after reset. For UTP with auto-negotiation ability, IEEE 802.3x flow control’s ability is auto-negotiated between the remote device and the RTL8305SC. If the auto-negotiation result of the 802.3x pause ability is ‘Enabled’ (Reg.4.10=1 and Reg.5.10=1), the full duplex 802 ...

Page 108

... Half Duplex Back Pressure If pin EnDefer is 1, the RTL8305SC will send a preamble to defer the other station’s transmission when there is no packet to send. Otherwise, if pin EnDefer is 0, the RTL8305SC will force a collision with the other station’s transmission when the buffer is full. ...

Page 109

... Address Search, Learning, and Aging When a packet is received, the RTL8305SC will use the least 10 bits of the destination MAC address to index the 1024-entry lookup table, and at the same time will compare the destination MAC address with the contents of the 16-entry CAM. If the indexed entry is valid, or the CAM comparison is matched, the received packet will be forwarded to the corresponding destination port. Otherwise, the RTL8305SC will broadcast the packet. This is the ‘ ...

Page 110

... Illegal Frame Illegal frames such as CRC error packets, runt packets (length < 64 bytes), and oversize packets (length > maximum length), will be discarded. 5-port 10/100Mbps Single-Chip Dual MII Switch Controller retransmission attempt is chosen as a uniformly distributed random integer 98 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 111

... Switch Core P0 P1 MAC MAC P0 P1 PHY PHY LAN 5-port 10/100Mbps Single-Chip Dual MII Switch Controller MAC MAC MAC P4_MII PHY PHY PHY Figure 4. Traditional Application 99 RTL8305SC Datasheet CPU with Dual MII MII_1 MII_2 Single PHY WAN Track ID: JATR-1076-21 Rev. 1.2 ...

Page 112

... The RTL8305SC has pin 42, DISDUALMII, to support both port 4 PHY and MAC circuits. When the Dual MII feature is enabled, the port 4 PHY may be used as the WAN interface as shown in Figure 5. RTL8305SC Switch Core P0 P1 MAC MAC P0 P1 PHY PHY LAN Dual MII Interfaces Configuration Port 4 of the RTL8305SC is able to separate the MAC and PHY circuits via the DISDUALMII configuration ...

Page 113

... PHY Mode MII Interface of 100Base-FX Mode 101 RTL8305SC Datasheet PHY Mode MII Interface MAC1_TXC MAC1_CRS MAC1_TXEN 4 MAC1_TXD[3:0] MAC1_RXC MAC1_RXDV 4 MAC1_RXD[3:0] MAC1_COL CPU/ Processor/ Routing Engine MAC2_RXC ...

Page 114

... RTL8305SC 51-MTXC/PRXC 52-MTXEN/PRXDV 54-MTXD[0]/PRXD[0] 59-MRXC/PTXC 60-MRXDV/PTXEN 61-MRXD[0]/PTXD[0] 58-MCOL/PCOL 81-PHY2RXC 80-PHY2RXDV 78~76, 73-PHY2RXD[3:0] 82-PHY2TXC 83-PHY2TXEN 88, 86~84-PHY2TXD[3:0] 89-PHY2COL PHY Mode MII Interface 102 RTL8305SC Datasheet MAC Mode MII Interface 1 MAC1_RXC MAC1_CRS MAC1_RXDV 4 MAC1_RXD[3:0] MAC1_TXC MAC1_TXEN 4 MAC1_TXD[3:0] MAC1_COL CPU/ Processor/ Routing Engine MAC2_RXC ...

Page 115

... The PHY circuit of UTP mode only supports full ability NWay (Flow control enabled, both 10/100Mbps, both Full/Half duplex). The RTL8305SC support four status pins to provide the link status or initial configuration for the MAC circuit. A brief description of the function follows: • ...

Page 116

... Reg. 5.10=Reg. 4.10 Reg. 5.8~5.5= Reg. 4.8~4.5 After Reset: Reg. 0.13=1 (Speed=100M) Reg. 0.12=0 (NWay=Disable) Reg. 0.8=Configurable Reg. 1.2=Signal detection Reg. 4.10=Configurable Reg. 4.8~4.5=1111 Reg. 5.10=Reg. 4.10 Reg. 5.8~5.5=Reg. 4.8~4.5 104 RTL8305SC Datasheet PHY5 Port 4 LED (Reg0 Upon Reset: Port 4 MAC Reg. 0.13=P4SPDSTA Reg. 0.12=P4ANEG Reg. 0.8=P4DUPSTA Reg ...

Page 117

... After Reset: Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable Reg. 5.10 and 5.8~5.5= Keep the contents identical to Reg. 4.10 and 4.8~4.5. 105 RTL8305SC Datasheet PHY5 Port 4 LED (Reg0 Port 4 MAC P4 P4 SPDSTA DUPSTA ...

Page 118

... After Reset: Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable Reg. 5.10 and 5.8~5.5= Keep the contents identical to Reg. 4.10 and 4.8~4.5. 106 RTL8305SC Datasheet PHY5 Port 4 LED (Reg0 Port 4 MAC P4 P4 SPDSTA DUPSTA ...

Page 119

... After Reset: Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5 107 RTL8305SC Datasheet PHY5 Port 4 LED (Reg0 Port 4 PHY Reg SPDSTA DUPSTA 1111 ...

Page 120

... Reg. 4.10=Configurable Reg. 0.13=Configurable Reg. 4.8~4.5=1111 Reg. 0.12=Configurable Reg. 5.10=Reg. 4.10 Reg. 0.8=Configurable Reg. 5.8~5.5=1111 Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5 108 RTL8305SC Datasheet PHY5 Port 4 LED (Reg0 Fiber Reg SPDSTA DUPSTA 1111 1 ...

Page 121

... After Reset: Reg. 0.13=Configurable Reg. 0.12=Configurable Reg. 0.8=Configurable Reg. 1.2=P4LNKSTA# Reg. 4.10 and 4.8~4.5= Configurable Reg. 5.10 and 5.8~5.5=Keep the contents identical to Reg. 4.10 and 4.8~4.5 109 RTL8305SC Datasheet PHY5 Port 4 LED (Reg0 Port 4 PHY Reg SPDSTA DUPSTA 1111 ...

Page 122

... Auto-Negotiation for UTP The RTL8305SC obtains the states of duplex, speed, and flow control ability for each port in UTP mode through the auto-negotiation mechanism defined in the IEEE 802.3u specifications. During auto- negotiation, each port advertises its ability to its link partner and compares its ability with advertisements received from its link partner ...

Page 123

... Note: In compliance with IEEE 802.3u, 100Base-FX does not support Auto-Negotiation. In order to operate correctly, both sides of the connection should be set to the same duplex and flow control ability. 5-port 10/100Mbps Single-Chip Dual MII Switch Controller 111 Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 124

... FEFI stream pattern, the following condition needs to be satisfied; the incoming signal causes link failure, which in turn causes the remote side to detect a Far-End-Fault. This means that the receive path has a problem from the view of the RTL8305SC. The FEFI mechanism is used only in 100Base-FX. ...

Page 125

... When Optical Receiving Fiber is disconnected from RTL8305SC, the FEFI cannot be detected by the RTL8305SC and also cannot be reflected on PHY Reg.1.4 since there is no FEFI. If there is a FEFI before Optical Receiving Fiber is disconnected, Reg.1.4 should be kept on 1. This bit should be cleared to 0 after it is read (read and clear) ...

Page 126

... If a port is connected NIC with MDI-X interface with a crossover cable, the RTL8305SC will reconfigure the port to ensure proper connection. This replaces the DIP switch commonly used for reconfiguring a port on a hub or switch ...

Page 127

... EEPROM. Soft Reset: Write bit12 of Reg16 of PHY0 as 1. The RTL8305SC resets all except PHY and does not load EEPROM and Pin Registers with serial EEPROM and Pins. The SoftReset, EEPROM, and Pin registers are designed to provide a convenient way for users who want to use SMI to change the configuration ...

Page 128

... The serial EEPROM shares two pins, SCL_MDC and SDA_MDIO, with SMI, and is optional for advanced configuration. SCL_MDC and SDA_MDIO are tri-state during hardware reset (pin RESET#=0). The RTL8305SC will try to automatically find the serial EEPROM upon reset only if pin EnEEPROM=1. If the first byte of the serial EEPROM is not 0xFF (NoEEPROM bit of the first byte=0), the RTL8305SC will load all contents of the serial EEPROM into internal registers ...

Page 129

... Random Read: A random read requires a ‘dummy’ byte write sequence to load in the data word address. Sequential Read: For the RTL8305SC, the sequential reads are initiated by a random address read. After the 24LC02 receives a data word, it responds with an acknowledgement. As long as the 24LC02 receives an acknowledgement, it will continue to increment the data word address and clock out sequential data words in series ...

Page 130

... Data n R/W ACK 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Start Word Address n ACK ACK Figure 13. Random Read ACK Data n+1 ACK Figure 14. Sequential Read 118 RTL8305SC Read Device Address Data n ACK ACK Data n+x ACK Track ID: JATR-1076-21 Rev. 1.2 Datasheet Stop NO ACK Stop NO ACK ...

Page 131

... PHY and internal registers (SMI slave mode: MDC is input). MDC is an input clock for the RTL8305SC to latch MDIO on its rising edge. The clock can run from DC to 25MHz. MDIO is a bi-directional connection used to write data to, or read data from the RTL8305SC. The PHY address is from ...

Page 132

... VLAN association. All the packets received on a given input port will be forwarded to this port’s VLAN members. The RTL8305SC supports five VLAN indexes for each port to individually index this port to one of the 16 VLAN membership registers. These 16 VLAN membership registers, VLAN ID [A] membership bit [4:0] ~ VLAN ID [P] membership bit [4:0], describe which ports are the members of this VLAN ...

Page 133

... IEEE 802.1Q Tagged-VID Based VLAN The RTL8305SC supports 16 VLAN entries to perform 802.1Q tagged-VID based VLAN mapping. In 802.1Q VLAN mapping, the RTL8305SC uses a 12-bit explicit identifier in the VLAN tag to associate received packets with a VLAN. The 16 groups of VLAN membership registers, ‘VLAN ID [A] membership [4:0] ~ VLAN ID [P] membership [4:0]’, consist of the ports that are in the same VLAN corresponding to the registers defined in register ‘ ...

Page 134

... VLAN tagged packets with a specific PVID only. When this function is enabled, packets with an incorrect PVID, and non-tagged packets will be dropped. The RTL8305SC uses an internal register, Port n VLAN index [3:0,] to index to one of the 16 VLAN entries. The VLAN ID associated with this indexed VLAN entry is the PVID for this port. Users may select VLAN insert/remove type insert a PVID on egress packets ...

Page 135

... Lookup Table Access The RTL8305SC supports registers for the CPU to read or write an internal 1024-entry lookup table via the SMI interface. Before reading/writing from/to the internal forwarding table, the contents of internal register, Indirect Access Control [15:0] at PHY4 Register 16, should be filled correctly. In the write cycle, the user must assign the write data in register Indirect Access Data and 3 at PHY4 Register 17~20 first ...

Page 136

... Differentiated Services Codepoint (DSCP) priority information from the DS-field defined in RFC 2474. The DS field byte in IPv4 is a Type-of-Service (TOS) octet. The recommended DiffServ Codepoint is defined in RFC 2597 to classify the traffic into different service classes. The RTL8305SC extracts the codepoint value of DS-fields from IPv4 packets, and identifies the priority of the incoming IP packet ...

Page 137

... CRC field to fit the 64-byte minimum packet length of the IEEE 802.3 spec. The RTL8305SC will recalculate the FCS (Frame Check Sequence) if the frame has been changed. 8.3.12. Filtering/Forwarding Reserved Control Frame The RTL8305SC supports the ability to forward or drop the frames of the IEEE 802.1D specified reserved multicast addresses. Address ...

Page 138

... Broadcast Storm Control According to the latched value of the DISBRDCTRL pin upon reset, the RTL8305SC determines whether or not to proceed with broadcast storm control. Once enabled (DISBRDCTRL=0), after 64 consecutive broadcast packets (DID=FF-FF-FF-FF-FF-FF) are received by a particular port, this port will discard following incoming broadcast packets for approximately 800ms. Any non-broadcast packet can reset the time window and broadcast counter such that the scheme restarts ...

Page 139

... If a loop is detected, the LoopLED# will be ON (active low or high). The LED goes out when both RTL8305SC ports of the loop are unplugged. The Loop frame length is 64 bytes and its format is shown below. ...

Page 140

... Each port supports loopback of the MAC (return to external device) for diagnostic purposes. Example 1: If the internal register, PHY4 Reg.22.13=0 (Local loopback), the RTL8305SC will forward local and broadcast packets from the input of Port 4 to the output of Port 4, and drop unicast packets from the input of Port 4. Other ports can still forward broadcast or unicast packets to Port 4. Example 2: If the internal register, PHY3 Reg.22.13=0 (Local loopback), the RTL8305SC will “ ...

Page 141

... This function is especially useful for diagnostic purposes. For example, a NIC can be used to send broadcast frames into port0 of the RTL8305SC and set Port1 to Reg0.14 Loopback. The frame will be looped back to port 0, so the received packet count can be checked to verify that the switch device is good ...

Page 142

... LED Pin 10K ohm Spd: Input=Pull-down, Active High. Bi-color Link/Act: The active status of LED_ADD is the opposite of LED_SPD and does not interact with input upon reset. Spd Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet 330 ohm Link/Act Flash Flash ...

Page 143

... Figure 22. Two Pin Bi-color LED for SPD Floating or Pull-high Figure 23. Two Pin Bi-color LED for SPD Pull-down 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Yellow LED_SPD Green Yellow LED_ADD Green 131 RTL8305SC Datasheet LED_ADD LED_SPD Track ID: JATR-1076-21 Rev. 1.2 ...

Page 144

... Power Generation The RTL8305SC can use a PNP transistor to generate 1.8V from a 3.3V power supply. This 1.8V is used for the digital core and analog receiver circuits. Do not use one PNP transistor for more than one RTL8305SC chip, even if the rating is enough. Use one transistor for each RTL8305SC chip. ...

Page 145

... Ambient Operating Temperature (Ta) 3.3V Vcc Supply Voltage Range (HVDD33, DVDD33) 1.8V Vcc Supply Voltage Range (DVDD18, AVDD18) 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 152. Electrical Characteristics/Ratings Min -0.5 -0.5 -0.5 Min -55 0 3.15 1.71 133 RTL8305SC Datasheet Max Units +4.0 V VDD V VDD V Max Units °C +150 °C +70 3. ...

Page 146

... Peak continuous 100% utilization 100Base-TX, idle 100Base-TX, Peak continuous 100% utilization Power saving Power down 10Base-T, idle 10Base-T, Peak continuous 100% utilization 100Base-TX, idle 100Base-TX, Peak continuous 100% utilization Power saving Power down 134 RTL8305SC Datasheet Min Typical Max Units 500 525 ...

Page 147

... Period of time from start of TP_IDL to link pulses or period of time between link pulses Peak output current on TD short circuit for 10 seconds. Terminate each end with 50Ω resistive load dB below fundamental, 20 cycles of all ones data TP_IDL width 135 RTL8305SC Datasheet Min Typical Max Units 1.007 V 99 ...

Page 148

... PHY2PRXDV, PCOL, PHY2PCOL, MDIO Figure 26. Transmission Data Timing of MII/SNI/SMI Interface 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Table 153. LED Timing LED Timing cyc os oh 136 RTL8305SC Min Typical Max 43 120 43 120 h Track ID: JATR-1076-21 Rev. 1.2 Datasheet Units ms ms ...

Page 149

... Output Hold time from MTXC/PRXC rising edge to MTXD[3:0]/PRXD[3:0], PHY2PRXD[3:0], MTXEN/PRXDV, PHY2PRXDV MCOL/PCOL, PHY2PCOL MRXD[3:0]/PTXD[3:0], MRXDV/PTXEN to s MRXC/PTXC rising edge setup time MRXD[3:0]/PTXD[3:0], MRXDV/PTXEN to h MRXC/PTXC rising edge hold time 137 RTL8305SC Datasheet I/O Min Type Max Units I ns 40±50 ppm I ns 400± ...

Page 150

... MRXD[0]/PTXD[0], MRXDV/PTXEN to s MRXC/PTXC rising edge setup time MTXD[0]/PRXD[0], MRXDV/PTXEN to h MRXC/PTXC rising edge hold time SMI Timing MDC clock cycle Write cycle s Write cycle h Read cycle 138 RTL8305SC Datasheet I/O Min Type Max Units O ns 100±50 ppm ...

Page 151

... Table 155. Package Description Parameter QFP128 RTL8305SC 2.85 mm Table 156. PCB Description Parameter layers (80 trace coverage of top/bottom layer) Table 157. Assembly Material Material Thermal Conductivity K (w/m-k) Silicon 147 C7025 168 AG03*7 2.0 6300HG 0.63 FR4 0.21 Cu 393 139 RTL8305SC Datasheet Track ID: JATR-1076-21 Rev. 1.2 ...

Page 152

... Single-Chip Dual MII Switch Controller Table 158. Simulation Analysis Conditions Parameter m/s Power=1.386 W 60°C Table 159. Results 0 1 117.3 112.1 111.0 104.7 41.3 37.6 4.51 5.33 140 RTL8305SC Datasheet 2 3 109.6 108.2 101.8 100.2 35.8 34.8 5.61 5.79 Track ID: JATR-1076-21 Rev. 1.2 ...

Page 153

... Pulse Magnetic 1 Two types of transformers are generally used for the RTL8305SC. One is a Quad (4 port) transformer with one common pin on both sides for an internal connected central tap. Another is a Single (1 port) transformer with two pins on both sides for a separate central tap. ...

Page 154

... Figure 28. UTP Application for Transformer with Separate Central Tap 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Pulse H1102 Transformer 50Ω 1% 1.8V 1:1 0.1uF 50Ω 1% AGND 1:1 50Ω 1.8V 1% 0.1uF 50Ω 1% AGND 1.96ΚΩ, 1% AGND 142 RTL8305SC Datasheet RJ-45 1 75Ω 75Ω 75Ω 75Ω 50pF/2KV Chassis GND Track ID: JATR-1076-21 Rev. 1.2 ...

Page 155

... Application The following is an example of an RTL8305SC connecting to a 3.3V fiber transceiver application circuit with a SIEMENS V23809-C8-C10 (3.3V~5V fiber transceiver, 1*9 SC Duplex Multimode 1300 nm LED Fast Ethernet/FDDI/ATM Optical Transceiver Module). RXIP RXIN RTL8305SC TXON TXOP 130Ω Figure 29. 100Base-FX with 3.3V Fiber Transceiver Application 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Fiber_RX_3 ...

Page 156

... Figure 30 shows an example of an RTL8305SC connected fiber transceiver application circuit with a SIEMENS V23809-C8-C10 (3.3V~5V fiber transceiver, 1*9 SC Duplex Multimode 1300nm LED Fast Ethernet/FDDI/ATM Optical Transceiver Module). RXIP RXIN RTL8305SC TXON TXOP Figure 30. 100Base-FX with 5V Fiber Transceiver Application 5-port 10/100Mbps Single-Chip Dual MII Switch Controller Fiber_RX_5V 82Ω ...

Page 157

... Use a bulk capacitor (4.7µF-10µF) between the collector of the PNP transistor and the ground plane. • Do not use one PNP transistor for more than one RTL8305SC chip, even if the rating is enough. Use one transistor for each RTL8305SC chip. 5-port 10/100Mbps Single-Chip Dual MII Switch Controller 145 Track ID: JATR-1076-21 Rev ...

Page 158

... Use 0.1µF decoupling capacitors and bulk capacitors between each power plane and the ground plane. • Power line connects from the source to the RTL8305SC pin should be at least 10 mil wide. Ground Plane • Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer to the rest of the board. • ...

Page 159

... Mechanical Dimensions See the Mechanical Dimensions notes on the next page. 5-port 10/100Mbps Single-Chip Dual MII Switch Controller 147 Track ID: JATR-1076-21 Rev. 1.2 RTL8305SC Datasheet ...

Page 160

... General appearance spec. Should be based on final visual 0.12 0.22 0.32 inspection. 0.05 0.15 0.25 13.75 14.00 14.25 19.75 20.00 20.25 0.25 0.5 0.75 16.90 17.20 17.50 APPROVE 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 CHECK - - 0.10 0° - 12° Table 161. Ordering Information Package 128-pin PQFP 128-pin PQFP Lead (Pb)-Free package 148 RTL8305SC TITLE: PQFP-128 -CU L/F, FOOTPRINT 3.2 mm LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. Q128 - 1 DATE 12 February 2003 REALTEK SEMICONDUCTOR CORP. Status Track ID: JATR-1076-21 Rev. 1.2 Datasheet 1.2 ...

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