EM638165TS-7 ETRON, EM638165TS-7 Datasheet

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EM638165TS-7

Manufacturer Part Number
EM638165TS-7
Description
143MHz 4M x 16 synchronous DRAM (SGRAM)
Manufacturer
ETRON
Datasheet

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Features
Overview
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
system can choose the most suitable modes to
maximize its performance. These devices are well
suited
bandwidth
performance PC applications.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
Fast access time from clock: 5/6/6/6/7 ns
Fast clock rate: 166/143/133/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
The EM638165 SDRAM is a high-speed CMOS
The EM638165 provides for programmable Read
By having a programmable mode register, the
for
and
applications
0.3V power supply
particularly
requiring
well
FAX: (886)-3-5778671
suited
4Mega x 16 Synchronous DRAM (SDRAM)
high
to
memory
high
Key Specifications
t
t
t
t
Ordering Information
CK3
AC3
RAS
RC
EM638165TS-6
EM638165TS-7
EM638165TS-7.5
EM638165TS-8
EM638165TS-10
A10/AP
Part Number
VDDQ
VDDQ
LDQM
VSSQ
VSSQ
CAS#
RAS#
WE#
Clock Cycle time(min.)
Access time from CLK(max.)
Row Active time(max.)
Row Cycle time(min.)
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDD
VDD
CS#
BA0
BA1
Pin Assignment (Top View)
A0
A1
A2
A3
EM638165
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Preliminary (Rev 0.6, 2/2001)
Frequency
166MHz
143MHz
133MHz
125MHz
100MHz
EM638165
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
42/45/45/48/50 ns
60/63/68/70/80 ns
-
5/5.4/5.4/6/7 ns
6/7/7.5/8/10 ns
6/7/7.5/8/10
Package
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II

Related parts for EM638165TS-7

EM638165TS-7 Summary of contents

Page 1

... VDD Key Specifications t Clock Cycle time(min.) CK3 t Access time from CLK(max.) AC3 t Row Active time(max.) RAS t Row Cycle time(min.) RC Ordering Information Part Number EM638165TS-6 EM638165TS-7 EM638165TS-7.5 high memory suited to high EM638165TS-8 EM638165TS-10 EM638165 Preliminary (Rev 0.6, 2/2001 VSS 2 53 DQ15 3 52 ...

Page 2

Block Diagram CLOCK CLOCK CLOCL BUFFER BUFFER CKE CS RAS CAS LDQM ...

Page 3

Pin Descriptions Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input ...

Page 4

WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command ...

Page 5

Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode ...

Page 6

Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0,1 signals. By latching the row address A11 ...

Page 7

COMMAND READ A NOP CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Burst Read Operation The read data appears on the DQs subject to the values on the DQM inputs two ...

Page 8

CLK DQM COMMAND NOP NOP CAS# latency=2 t CK2 , DQ's : "H" or "L" Read to Write Interval CLK DQM COMMAND NOP NOP CAS# latency=2 t CK2 , DQ's : "H" or "L" ...

Page 9

Write command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active ...

Page 10

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals t signals must be used to mask ...

Page 11

CK2 CKE CS# RAS# CAS# WE# A11 A10 A0-A9 DQM Hi-Z DQ Mode Register Set Cycle The mode register is divided into various fields depending on functionality. Address BS0,1 A11,10 Function RFU* RFU* *Note: RFU (Reserved ...

Page 12

Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. A3 Burst Type 0 Sequential 1 Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the ...

Page 13

Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation Write Burst Length (A9) This bit is used to select the ...

Page 14

Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No ...

Page 15

Absolute Maximum Rating Symbol Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Operating Temperature OPR T Storage Temperature STG T Soldering Temperature (10 second) SOLDER P Power Dissipation D I Short ...

Page 16

Recommended D.C. Operating Conditions (V Description/Test condition Operating Current t t (min), Outputs Open RC RC Precharge Standby Current in non-power down mode t = 15ns, CS# V (min), CKE Precharge Standby Current in non-power down mode ...

Page 17

Electrical Characteristics and Recommended A.C. Operating Conditions = 3.3V¡ Ó 0 .3V -40~85°C) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t RAS# to CAS# delay RCD (same bank) ...

Page 18

A.C. Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals Output 30pF LVTTL D.C. Test Load (A) 7. Transition times are ...

Page 19

Timing Waveforms Figure 1. AC Parameters for Write Timing CLK CK2 CKE CS# RAS# CAS# WE# BA0 A10 RAx t IS ...

Page 20

Figure 2. AC Parameters for Read Timing CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx t IS A0-A9,A11 RAx DQM Hi-Z DQ Activate Command Bank A ...

Page 21

Figure 3. Auto Refresh (CBR CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9,A11 t RP DQM DQ PrechargeAll AutoRefresh Command Command Preliminary (Burst Length=4, CAS# Latency= ...

Page 22

Figure 4. Power on Sequene and Auto Refresh (CBR CLK t CK2 CKE High level is reauired CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9,A11 DQM Hi-Z PrechargeALL 1st AutoRefresh ...

Page 23

Figure 5. Self Refresh Entry & Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# RAS# *Note 8 CAS# BA0,1 A0-A9,A11 WE # DQM Hi-Z DQ Self Refresh Enter Note: To Enter SelfRefresh ...

Page 24

Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 RAx A10 A0-A9,A11 RAx CAx DQM DQ Hi-Z Ax0 Activate Clock Suspend ...

Page 25

Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 CAx RAx DQM Hi-Z DQ Activate Read Command Command ...

Page 26

Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 CAx RAx DQM Hi-Z DQ Activate Read Command ...

Page 27

Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 RAx CAx DQM DQ Hi-Z ...

Page 28

Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 RAx CAx DQM Hi-Z DQ DAx0 Activate Clock Suspend ...

Page 29

Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9,A11 RAx CAx DQM DQ Hi-Z DAx0 Activate Clock ...

Page 30

Figure 8. Power Down Mode and Clock Mask CLK t CK2 t IS CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx A0~A9,A11 DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A Power Down ...

Page 31

Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw RAw CAw A0~A9,A11 DQM Hi-Z DQ Aw0 Aw1 Aw2 Activate ...

Page 32

Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw CAw RAw A0~A9,A11 DQM Hi-Z DQ Activate Read Command Command ...

Page 33

Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw A0~A9,A11 CAw RAw DQM Hi-Z DQ Activate Read Command Command ...

Page 34

Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RBw CBw A0~A9,A11 RBw DQM Hi-Z DQ DBw0DBw1DBw2 Activate Command Bank ...

Page 35

Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 RBw A10 A0~A9,A11 RBw CBw DQM Hi-Z DBw0 DBw1 DBw2 DBw3 DBx0 ...

Page 36

Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS BA0,1 A10 RBw A0~A9,A11 RBw CBw DQM Hi-Z DQ DBw0 DBw1DBw2 DBw3 ...

Page 37

Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS# CAS# WE# BA0,1 RBx A10 RBx CBx A0~A9,A11 t RCD t DQM AC1 Hi-Z DQ Bx0 ...

Page 38

Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RBx A10 A0~A9,A11 RBx CBx t t RCD AC2 DQM Hi-Z Bx0 DQ ...

Page 39

Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 A10 RBx RBx A0~A9,A11 CBx t t RCD DQM Hi-Z DQ Activate Read ...

Page 40

Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS# CAS# WE# BA0,1 A10 RAx A0~A9,A11 RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 ...

Page 41

Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 ...

Page 42

Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 t RCD DQM Hi-Z DQ DAx0 DAx1 DAx2 ...

Page 43

Figure 13.1. Read and Write Cycle CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 DQM Hi-Z DQ Ax0 Ax1 Activate Command Bank A Read Command Bank A Preliminary ...

Page 44

Figure 13.2. Read and Write Cycle CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Preliminary (Burst Length=4, ...

Page 45

Figure 13.3. Read and Write Cycle CLK t CK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx CAx RAx A0~A9,A11 DQM Hi-Z DQ Read Activate Command Command Bank A Bank A Preliminary (Burst Length=4, ...

Page 46

Figure 14.1. Interleaving Column Read Cycle CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RAx A0~A9,A11 t t AC1 RCD DQM Hi-Z DQ Ax0 Ax1 Ax2 Activate Command Bank A ...

Page 47

Figure 14.2. Interleaving Column Read Cycle CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx CAy RAx A0~A9,A11 t t RCD AC2 DQM Hi-Z DQ Activate Read Command Command Bank A Bank ...

Page 48

Figure 14.3. Interleaved Column Read Cycle CLK t CK3 CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx CAx A0~A9,A11 t RCD DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Preliminary ...

Page 49

Figure 15.1. Interleaved Column Write Cycle CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBw RAx CAx RBw A0~A9,A11 t RCD DQM t RRD Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate ...

Page 50

Figure 15.2. Interleaved Column Write Cycle CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 t RCD DQM t RRD Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Write Command ...

Page 51

Figure 15.3. Interleaved Column Write Cycle CLK t CK3 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx RBw A0~A9,A11 t RCD DQM t > t RRD RRD(min) Hi-Z DQ DAx0 DAx1 DAx2 ...

Page 52

Figure 16.1. Auto Precharge after Read Burst CLK t CK1 High CKE CS# RAS# CAS# WE# BA0,1 RAx RBx A10 RBx CBx RAx CAx A0~A9,A11 DQM Hi-Z DQ Ax1 Ax2 Ax0 Activate Activate Command ...

Page 53

Figure 16.2. Auto Precharge after Read Burst CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RAx RBx A10 RAx RBx CAx A0~A9,A11 DQM Hi-Z DQ Ax0 Activate Read Activate Command Command Command ...

Page 54

Figure 16.3. Auto Precharge after Read Burst CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RBx CAx RAx RBx A0~A9,A11 DQM Hi-Z DQ Activate Activate Command Command Bank A Bank ...

Page 55

Figure 17.1. Auto Precharge after Write Burst CLK t CK1 High CKE CS# RAS# CAS# WE# BA0,1 RAx RBx A10 RBx RAx CAx A0~A9,A11 DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Activate Write ...

Page 56

Figure 17.2. Auto Precharge after Write Burst CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RAx RBx A10 CAx A0~A9,A11 RAx RBx DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Write Activate ...

Page 57

Figure 17.3. Auto Precharge after Write Burst CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 RBx RAx A9 RAx CAx RBx A0~A9,A11 DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 Activate Activate Command ...

Page 58

Figure 18.1. Full Page Read Cycle CLK t CK1 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RBx RBx A0~A9,A11 RAx CAx t RRD DQM Hi-Z DQ Ax+1 Ax+2 Ax Activate Activate Command ...

Page 59

Figure 18.2. Full Page Read Cycle CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RBx A10 RAx RAx CAx RBx A0~A9,A11 DQM Hi Activate Read Activate Command Command Command Bank ...

Page 60

Figure 18.3. Full Page Read Cycle CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx CAx A0~A9,A11 DQM Hi-Z DQ Activate Read Command Command Bank A Bank A Preliminary (Burst ...

Page 61

Figure 19.1. Full Page Write Cycle CLK t CK1 High CKE CS# RAS# CAS# WE# BA0,1 RBx RAx A10 RAx CAx RBx A0~A9,A11 DQM Hi-Z DQ DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx-1 ...

Page 62

Figure 19.2. Full Page Write Cycle CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RAx RBx A10 RAx CAx A0~A9,A11 RBx DQM Hi-Z DQ DAx DAx+1 DAx+2 DAx+3 DAx-1 Activate Write Activate ...

Page 63

Figure 19.3. Full Page Write Cycle CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx CAx A0~A9,A11 DQM Hi-Z DQ DAx DAx+1 Activate Write Command Command Command Bank A Bank ...

Page 64

Figure 20. Byte Write Operation CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx A0~A9,A11 CAx LDQM UDQM DQ0 - DQ7 Ax0 DQ8 - DQ15 Upper 3 Bytes Activate Read ...

Page 65

Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= CLK t CK1 High CKE Begin Auto Precharge Bank B CS# RAS# CAS# WE# BA0,1 RAu RBu RBv A10 CBu RAu CAu RBv ...

Page 66

Figure 22. Full Page Random Column Read CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx RAx RBx CAx A0~A9,A11 DQM t t RRD RCD DQ Activate Activate Command Command Command ...

Page 67

Figure 23. Full Page Random Column Write CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 RAx RBx A10 RAx RBx CAx A0~A9,A11 DQM t t RRD RCD DQ DAx0 DBx0DAy0 Activate Activate Command ...

Page 68

Figure 24.1. Precharge Termination of a Burst CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx CAx A0~A9,A11 DQM DQ DAx0 DAx1 DAx2 DAx3 DAx4 Activate Precharge Termination Command of a ...

Page 69

Figure 24.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx CAx A0~A9,A11 DQM DQ DAx0 DAx1 D ...

Page 70

Figure 24.3. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BA0,1 RAx A10 RAx CAx A0~A9,A11 t WR DQM DQ ...

Page 71

... EtronTech 54 Pin TSOP II Package Outline Drawing Information Symbol Dimension in inch Min Normal 0.002 0.00395 0.012 c 0.0047 0.0065 D 0.872 0.8755 E 0.3960 - 0.0315 e 0.462 HE 0.016 Notes: 1. Dimension D&E do not include interiead flash. 2. Dimension B does not include dambar protrusion/intrusion. ...

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