M12L16161A-7T ETC ETC, M12L16161A-7T Datasheet
M12L16161A-7T
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M12L16161A-7T Summary of contents
Page 1
... Range of operating fre- quencies, programmable burst length and pro- grammable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. M12L16161A-4.3T M12L16161A-5T M12L16161A-5.5T M12L16161A-6T M12L16161A-7T M12L16161A- DQ0 2 49 ...
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... SHZ Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. P.2 M12L16161A LWE LDQM DQi LDQM Publication Date : Jan. 2000 ...
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... 10ns acceptable. 10ns acceptable. + 0.3V, all other pins are not under test = 0V 1MHz) A Symbol Min C 2.5 CLK C 2 2.5 ADD C 4.0 OUT P.3 M12L16161A Unit Max Unit Note Max Unit 4 ...
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... (min), CLK V (max 0Ma, Page Burst CCD CCD t (min (min). CC P.4 M12L16161A (min)/V (max)=2.0V/0.8V) IL Version Unit Note -8 250 230 210 190 160 140 270 250 230 210 180 160 mA ...
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... RAS 100 t (max) RAS 47 (min (min) CDL t (min) RDL t (min) BDL t (min) CCD CAS latency=3 CAS latency=2 P.5 M12L16161A = Unit Vtt =1.4V è 50 è Z0= (Fig.2) AC Output Load Circuit Unit Note - ...
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... SLZ - SHZ - *All AC parameters are measured from half to half. P.6 M12L16161A - Unit Note 1000 ns 1000 1000 2.5 2 ...
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... M12L16161A-6T CAS Latency Frequency 166MHz(6.0ns) 3 143MHz(7.0ns) 3 125MHz(8.0ns) 2 111MHz(9.0ns) 2 100MHz(10.0ns) 2 M12L16161A-7T CAS Latency Frequency 143MHz(7.0ns) 3 125MHz(8.0ns) 3 111MHz(9.0ns) 2 100MHz(10.0ns) 2 83MHz(12.0ns) 2 M12L16161A-8T CAS Latency Frequency 125MHz(8.0ns) 3 111MHz(9.0ns) 3 100MHz(10 ...
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... Vender Specific Mode Register Set Burst length Wrap type Latency mode Mode Register Write P.8 M12L16161A v =Valid x =Don’t care Bit2-0 WT=0 WT=1 000 1 1 001 2 2 010 4 4 011 8 8 100 R R 101 R R 110 ...
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... P.9 Publication Date : Jan. 2000 M12L16161A Interleave Addressing Sequence (decimal Interleave Addressing Sequence (decimal ...
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... (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) t after the end of burst. RP P.10 M12L16161A DQM BA A10/AP A9~A0 Note CODE 1 Row Address 4 Column ...
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... P.11 M12L16161A *Note2 Publication Date : Jan. 2000 ...
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... Enable auto precharge, precharge bank A at end of burst Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA precharge 0 0 Bank Bank Both Banks Elite Semiconductor Memory Technology Inc. Operation P.12 Publication Date : Jan. 2000 M12L16161A Revision : 1.3u ...
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... Elite Semiconductor Memory Technology Inc P.13 M12L16161A ...
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... *Note4 SAC Prech Row Active (A-B ank) (A-Ba nk after the clock. SHZ (t t +CAS latency-1)+ RCD P.14 M12L16161A ...
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... Qa0 Qa1 Qb0 Qb1 Dc0 Qb2 Qa0 Qa1 Qb1 Qb2 Dc0 t CDL *Note1 Read Write (A-Bank) (A-Bank) t before Row precharge, will be written. RDL P.15 M12L16161A *Note2 Cd0 t RDL Dc1 Dd0 Dd1 Dc1 Dd0 Dd2 *Note3 Write Precharge (A-Bank) (A-Bank) : Don't care Publication Date : Jan ...
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... Elite Semiconductor Memory Technology Inc HIGH CAc CBb QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Read Read (B-Bank) (A-Bank) P.16 M12L16161A *Note2 CBd CAe Read Precharge Read (B-Bank) (A-Bank) (A-Bank) : Don't care Publication Date : Jan ...
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... HIGH CBb CAc DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 t CDL Write Write (B-Bank) (A-Bank) P.17 M12L16161A *Note2 CBd t RDL *Note1 Precharge (Both Banks) Write (B-Bank) : Don't care Publication Date : Jan. 2000 Revision : 1.3u ...
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... HIGH RBb CBb RBb RBb QAa1 QAa2 QAa3 DBb0 QAa1 QAa0 QAa2 QAa3 DBb0 Write Precharge (B-Bank) (A-Bank) Row Active (B-Bank) P.18 M12L16161A RAc CAc RAc *Note1 t CDL DBb1 DBb2 DBb3 QAc0 QAc1 DBb1 DBb2 ...
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... CL= 2 Auto Precharge Start Point ( A - Bank) CL= 3 Auto Precharge Start Point ( A - Bank) t before internal precharge start RAS P.19 M12L16161A ...
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... P.20 M12L16161A ...
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... P.21 M12L16161A ...
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... P.22 M12L16161A ...
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... Read with Auto Precharge (A-Bank) P.23 M12L16161A ...
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... Row Active Read Active Precharge Active Power-down Power-Down Power-down Exit Exit Entry P.24 M12L16161A Publication Date : Jan. 2000 ...
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... *Note3 * required before exit from self refresh. RAS P.25 M12L16161A Publication Date : Jan ...
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... Mode Register Set table. Elite Semiconductor Memory Technology Inc. Auto Refresh Cycle P.26 M12L16161A Publication Date : Jan ...
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... P.27 M12L16161A O (4X GAGE O (4X DETAIL WITH PLATING SECTION B-B BASE METAL b 1 Dimension in inch Nom Max - - 0.047 0.004 0.006 0.039 ...