VT8363A ETC-unknow, VT8363A Datasheet
VT8363A
Available stocks
Related parts for VT8363A
VT8363A Summary of contents
Page 1
'HOLYHULQJ ...
Page 2
WK http://www.viatech.com ...
Page 3
... Updated Device 0 register descriptions: Rx8, 54[5-4], 55[4], 56-58, 60, 63[1- 0], 67, 68[7,4-3,1-0], 69[7-6], 6C[5-4], 76[5-4], 79[7-3,0], 7B, 80[15-8], AC[6], AD[6-5], AF, B0[7], B2[3], B3, B5, B6[6-5], B8, F6 Updated Device 1 register descriptions: Rx2, 34, 44[5] Removed ambient temp spec and changed case operating temp spec Created separate table for power specs Fixed pin 1 orientation in mechanical diagram -i- KT133A - VT8363A Initials DH Revision History ...
Page 4
... Device 1 Header Registers - PCI-to-PCI Bridge ................................................................................................................ 41 Device 1 Configuration Registers - PCI-to-PCI Bridge..................................................................................................... 43 AGP Bus Control .................................................................................................................................................................................. 43 ELECTRICAL SPECIFICATIONS............................................................................................................................................... BSOLUTE AXIMUM ATINGS DC C ................................................................................................................................................................ 46 HARACTERISTICS P C ......................................................................................................................................................... 47 OWER HARACTERISTICS ...................................................................................................................................................... 47 IMING PECIFICATIONS MECHANICAL SPECIFICATIONS ............................................................................................................................................. 48 Preliminary Revision 0.1, October 9, 2000 T C ABLE OF ONTENTS ................................................................................................................................................. 46 -ii- KT133A - VT8363A Table of Contents ...
Page 5
... FIGURE 1. KT133A SYSTEM BLOCK DIAGRAM USING THE VT82C686A SOUTH BRIDGE........................................ 4 FIGURE 2. VT8363A KT133A BALL DIAGRAM (TOP VIEW) ................................................................................................ 6 FIGURE 3. CPU / SDRAM / AGP / PCI CLOCK CONNECTIONS ......................................................................................... 15 FIGURE 4. GRAPHICS APERTURE ADDRESS TRANSLATION ......................................................................................... 34 FIGURE 5. MECHANICAL SPECIFICATIONS - 552-PIN BALL GRID ARRAY PACKAGE ........................................... 48 Preliminary Revision 0.1, October 9, 2000 ...
Page 6
... TABLE 1. VT8363A KT133A PIN LIST (NUMERICAL ORDER)............................................................................................. 7 TABLE 2. VT8363A KT133A PIN LIST (ALPHABETICAL ORDER) ...................................................................................... 8 TABLE 3. VT8363A KT133A PIN DESCRIPTIONS.................................................................................................................... 9 TABLE 4. VT8363A REGISTERS ................................................................................................................................................ 17 TABLE 5. SYSTEM MEMORY MAP.......................................................................................................................................... 25 TABLE 6. MEMORY ADDRESS MAPPING TABLE ............................................................................................................... 25 TABLE 7. VGA/MDA MEMORY/IO REDIRECTION.............................................................................................................. 43 TABLE 8. AC TIMING MIN / MAX CONDITIONS.................................................................................................................. 47 Preliminary Revision 0 ...
Page 7
... High Performance and High Integration Athlon AGP 4x / PC133 Chipset with Advanced System Power Management KT133A Chipset: VT8363A system controller and VT82C686A PCI to ISA bridge Single chip Athlon system controller with 64-bit Socket-A Athlon CPU, 64-bit system memory, 32-bit PCI and 32- ...
Page 8
... Transaction timer for fair arbitration between PCI masters (granularity of two PCI clocks) Symmetric arbitration between Host/PCI bus for optimized system performance Complete steerable PCI interrupts PCI-2.2 compliant, 32 bit 3.3V PCI interface with 5V tolerant inputs Preliminary Revision 0.1, October 9, 2000 CPU Mode 100 MHz DDR 3x synchronous -2- KT133A - VT8363A Features ...
Page 9
... Suspend-to-DRAM and Self-Refresh operation SDRAM self-refresh power down 8 bytes of BIOS scratch registers Low-leakage I/O pads Built-in NAND-tree pin scan test capability 3.3V, 0.35um, high speed / low power CMOS process mm, 552 pin BGA Package Preliminary Revision 0.1, October 9, 2000 -3- KT133A - VT8363A Features ...
Page 10
... Figure 1. KT133A System Block Diagram Using the VT82C686A South Bridge The KT133A chip set consists of the VT8363A system controller (552 pin BGA) and the VT82C686A PCI to ISA bridge (352 pin BGA). The system controller provides superior performance between the CPU, DRAM, AGP bus, and PCI bus with pipelined, burst, and concurrent operation ...
Page 11
... Coupled with the VT82C686A south bridge chip, a complete power conscious PC main board can be implemented with no external TTLs. The KT133A chipset is ideal for high performance, high quality, high energy efficient and high integration desktop AGP / PCI / ISA computer systems. Preliminary Revision 0.1, October 9, 2000 -5- KT133A - VT8363A The Overview ...
Page 12
... REQ# SBA SBA SBA AE GND GND GD28 GD25 SBA AF SBS SBS# GD31 GD29 GD27 GD24 4 Preliminary Revision 0.1, October 9, 2000 Figure 2. VT8363A KT133A Ball Diagram (Top View DICLK D11# D0# D5# D7# D18# D20# 0# DOCLK D9# D3# GND D4# D6# GND D19# ...
Page 13
... Table 1. VT8363A KT133A Pin List (Numerical Order) Pin # Pin Name Pin # Pin Name A01 NC D03 NC A02 P GND D04 NC A03 O AIN14# D05 O CONNECT A04 O AINCLK# D06 P VTT A05 O AIN09# D07 O AIN06# A06 O AIN03# D08 I DOCLK0# A07 O AIN11# D09 P VTT A08 IO D11# ...
Page 14
... Table 2. VT8363A KT133A Pin List (Alphabetical Order) Pin # Pin Name Pin # Pin Name AC03 IO AD00 A09 IO D00# AC04 IO AD01 E11 IO D01# AC01 IO AD02 C10 IO D02# AC02 IO AD03 B09 IO D03# AB01 IO AD04 B11 IO D04# AB02 IO AD05 A11 IO D05# AA04 IO AD06 B12 ...
Page 15
... B15 DINVAL# Preliminary Revision 0.1, October 9, 2000 ESCRIPTIONS Table 3. VT8363A KT133A Pin Descriptions CPU Interface Signal Description O CLK Forward Reset. Reset the CLK forward circuitry for the Athlon™ interface. O Connect. Used for power management and CLK-forward initialization at reset. I Processor Ready. Used for power management and CLK-forward initialization at reset ...
Page 16
... Other PCB layouts (AT, LPX, and NLX) were also considered and can typically follow the same general component placement Five PCI Slots VT8231 South Bridge IDE Connectors Preliminary Revision 0.1, October 9, 2000 Socket-462 Athlon CPU AGP 1 26 Slot CPU 8363 PCI DRAM AGP DRAM Modules -10- KT133A - VT8363A Power Supply A … AF Pin Descriptions ...
Page 17
... Write Enable Command Indicator. (see Device 0 RxB6[5]) O Clock Enables. Clock enables for each DRAM bank for powering down the SDRAM or clock control for reducing power usage and for reducing heat / temperature in high-speed memory systems. -11- KT133A - VT8363A Settings 0=100, 1=66 1=Edge 0=Auto, ~0=Strap 0=Auto, ~0=Strap 0=11, 1=11 ...
Page 18
... Asserted by the target to request the master to stop the current Stop. transaction. IO Device Select. This signal is driven by the VT8363A when a PCI initiator is attempting to access main memory input when the VT8363A is acting as a PCI initiator. IO Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]. ...
Page 19
... Stop (PCI transactions only). Asserted by the target to request the master to stop the current transaction. Device Select (PCI transactions only). This signal is driven by the VT8363A when a PCI initiator is attempting to access main memory input when the VT8363A is acting as PCI initiator. Not used for AGP cycles. -13- ...
Page 20
... SBA port (to send addresses unmultiplexed). AGP masters implement one or the other or select one at initialization time (they are not allowed to change during runtime). Therefore only one of the two will be used and the signals associated with the other will not be used. Therefore the VT8363A has an internal pullup on GRBF# to maintain it in the de-asserted state in case it is not implemented on the master device. ...
Page 21
... I PCI Clock. This pin receives a buffered host clock divided-by-6 to create 33 MHz. This clock is used by all of the VT8363A logic that is in the PCI clock domain. This clock input must be 33 MHz maximum to comply with PCI specification requirements and must be synchronous with the host CPU clock, HCLK. The host CPU clock must lead the PCI clock by 1.5 ± ...
Page 22
... This can be provided with a resistive divider on VCC3 using 270 ohm and 180 ohm (2%) resistors. I AGP N Compensation. Connect to VCCQ through a 60 ohm resistor. I AGP P Compensation. Connect to GND through a 60 ohm resistor. I DFT In. I Scan Enable. I Scan In. O Scan Out. -16- KT133A - VT8363A Pin Descriptions ...
Page 23
... R EGISTERS Register Overview The following tables summarize the configuration and I/O registers of the VT8363A. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’ ...
Page 24
... VT8363A Device 0 Registers - Host Bridge Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status 8 Revision ID 9 Program Interface A Sub Class Code B Base Class Code C -reserved- D Latency Timer E Header Type F Built In Self Test (BIST) 13-10 Graphics Aperture Base 14-2B -reserved- 2D-2C Subsystem Vendor ID ...
Page 25
... F7 Foundry DRAM Arbitration Timer 00 — F9-FB -reserved- FC Back-Door Control 1 FD Back-Door Control 2 Default Acc strapping RO FF-FE Back-Door Device ID strapping — -19- KT133A - VT8363A — — ...
Page 26
... VT8363A Device 1 - PCI-to-PCI Bridge Header Registers Offset Configuration Space Header 1-0 Vendor ID 3-2 Device ID 5-4 Command 7-6 Status 8 Revision ID 9 Program Interface A Sub Class Code B Base Class Code C -reserved- D Latency Timer E Header Type F Built In Self Test (BIST) 10-17 -reserved- 18 Primary Bus Number 19 Secondary Bus Number ...
Page 27
... Miscellaneous I/O One I/O port is defined in the VT8363A: Port 22. Port 22 – PCI / AGP Arbiter Disable ..............................RW 7-2 Reserved ........................................ always reads 0 1 AGP Arbiter Disable 0 Respond to GREQ# signal .....................default 1 Do not respond to GREQ# signal 0 PCI Arbiter Disable 0 Respond to all REQ# signals..................default 1 Do not respond to any REQ# signals, including ...
Page 28
... CF8 / CFC with bus number, function number, and device number equal to zero. Device 0 Offset 1-0 - Vendor ID (1106h) ..........................RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Device 0 Offset 3-2 - Device ID (0305h)............................RO 15-0 ID Code (reads 0305h to identify the VT8363A) Device 0 Offset 5-4 –Command (0006h) ..........................RW 15-10 Reserved ........................................ always reads 0 9 Fast Back-to-Back Cycle Enable ...
Page 29
... Device 0 Offset 37-34 - Capability Pointer (000000A0h) RO Contains an offset from the start of configuration space. 31-0 AGP Capability List Pointer ........ always reads A0h (This Register (Gr Aper Size 16M 0 0 32M 0 0 64M 0 0 128M 0 0 256M -23- KT133A - VT8363A Device 0 Register Descriptions ...
Page 30
... Disable................................................... default 1 Enable 2 PCI Master Pipeline Request 0 Disable................................................... default 1 Enable 1 PCI-to-CPU / CPU-to-PCI Concurrency 0 Disable................................................... default 1 Enable 0 Fast Write-to-Read Turnaround 0 Disable................................................... default 1 Enable Device 0 Offset 55 – Debug .............................................. RW Reserved (do not program)......................default = 0 7-0 -24- Device 0 Register Descriptions KT133A - VT8363A (P2C / C2P) ...
Page 31
... Some of these registers, however, may need to be programmed using specific sequences during power-up initialization to properly detect the type and size of installed memory (refer to the VIA Technologies VT8363A BIOS porting guide for details). Table 5. System Memory Map Space Start ...
Page 32
... CAS Latency reserved 3 DIMM Type 0 Standard 1 Registered ............................................. default 2 SDRAM: ACTIVE Command to CMD Command .................................................... default 2 VCM SDRAM: Prefetch Read Latency .................................................... default 1-0 Bank Interleave 00 No Interleave ......................................... default 01 2-way 10 4-way 11 Reserved -26- Device 0 Register Descriptions KT133A - VT8363A ...................................... default ...
Page 33
... Fast DRAM Precharge for Different Bank 0 Disable................................................... default 1 Enable 2 DRAM 4K Page Enable (for 64Mbit DRAM) 0 Disable................................................... default 1 Enable 1 DIMM Type 0 Unbuffered............................................. default 1 Registered 0 AutoPrecharge on CPU Writeback / TLB Lookup 0 Disable................................................... default 1 Enable -27- Device 0 Register Descriptions KT133A - VT8363A CPU / DRAM 100 / 100 100 / 133 133 / 133 (def) -reserved- ...
Page 34
... Normal slew rate control........................ default 1 More slew rate control 1 AGP Pad Slew Rate Control 0 Disable................................................... default 1 Enable 0 Multi-Page Open 0 Disable (page registers marked invalid and no page register update which causes non page- mode operation) 1 Enable ................................................... default -28- Device 0 Register Descriptions KT133A - VT8363A ...
Page 35
... Delay DRAM Read Latch 4 Memory Data Drive (MD, MECC) 3 SDRAM Command Drive (SRAS#, SCAS#, SWE#) 2 Memory Address Drive (MA, WE#) are generated on 1 CAS# Drive 0 RAS# Drive -29- KT133A - VT8363A 0 Disable................................................... default 1 Enable 00 No Delay................................................ default .................................................... default 16mA .................................................... default ...
Page 36
... PCI bus and non-burstable won’t. This is the normal setting. 2 PCI Fast Back-to-Back Write 0 Disable................................................... default 1 Enable 1 Quick Frame Generation 0 Disable................................................... default 1 Enable 0 1 Wait State PCI Cycles 0 Disable................................................... default 1 Enable -30- Device 0 Register Descriptions KT133A - VT8363A ...
Page 37
... CPU/PCI Master Latency Timer Control 00 AGP master reloads MLT timer ............ default 01 AGP master falling edge reloads MLT timer 10 AGP master rising edge resets timer to 00 and AGP master falling edge reloads MLT timer 11 Reserved (do not program) -31- Device 0 Register Descriptions KT133A - VT8363A ...
Page 38
... REQn# to REQ4# Mapping 00 REQ4# 01 REQ0# 10 REQ1# 11 REQ2# 1 CPU QW or High DW Read Accesses to PCI Slave Allowed To Be Backed Off 0 Disable................................................... default 1 Enable 0 REQ4# Is High Priority Master 0 Disable................................................... default 1 Enable Device 0 Offset 77 - Chip Test Mode (00h)..................... RW Reserved (do not use) .................................default=0 7-0 -32- Device 0 Register Descriptions KT133A - VT8363A ...
Page 39
... Reserved 1 PCI Master Access Head / Tail Select 0 Tail .................................................... default 1 Head ........................................always reads 0 0 Reserved Device 0 Offset 7E – DLL/PLL Test Mode 1 (00h) ........ RW 7-0 Reserved (do not use) .................................default=0 Device 0 Offset 7F – DLL/PLL Test Mode 2 (00h) ........ RW 7-0 Reserved (do not use) .................................default=0 -33- Device 0 Register Descriptions KT133A - VT8363A ...
Page 40
... Since address translation using the above scheme requires an access to system memory, an on-chip cache (called a "Translation Lookaside Buffer" or TLB) is utilized to enhance performance. The TLB in the VT8363A contains 16 entries. Address "misses" in the TLB require an access of system memory to retrieve translation data. Entries in the TLB are replaced using an LRU (Least Recently Used) algorithm ...
Page 41
... Note: To disable the Graphics Aperture, set this bit to 0 and set all bits of the Graphics Aperture Size enable the Graphics Aperture, set this bit to 1 and program the Graphics Aperture Size to the desired aperture size. 0 Reserved ........................................always reads 0 -35- Device 0 Register Descriptions KT133A - VT8363A ...
Page 42
... Reserved 5 4G Enable 0 Disable................................................... default 1 Enable 4 Fast Write Enable 0 Disable................................................... default 1 Enable 3 Reserved ...................................... always reads Mode Enable 0 Disable................................................... default 1 Enable 1 2X Mode Enable 0 Disable................................................... default 1 Enable 0 1X Mode Enable 0 Disable................................................... default 1 Enable -36- Device 0 Register Descriptions KT133A - VT8363A ...
Page 43
... Rate Supported 0 4x Rate not supported ............................ default 1 4x Rate supported 1-0 Reserved ........................................always reads 0 Device 0 Offset AF – AGP Strobe Drive Strength ......... RW 7-4 AGP Strobe Output Buffer Drive Strength N Ctrl 3-0 AGP Strobe Output Buffer Drive Strength P Ctrl -37- Device 0 Register Descriptions KT133A - VT8363A ...
Page 44
... GD[31:16] delayed Reserved ........................................always reads 0 2 AGP Preamble Control 0 Disable................................................... default 1 Enable 1 AGP Voltage 0 1.5V .................................................... default 1 3.3V 0 GDS Output Delay 0 None .................................................... default 1 GDS[1-0] & GDS[1-0]# delayed by 0.4 ns (GDS1 & GDS1# will be delayed an additional 1ns if bit -38- Device 0 Register Descriptions KT133A - VT8363A ...
Page 45
... Device 0 Offset B8 – S2K Compensation Result 4 .......... RO 7 S2K Compensation Circuit Trigger 6 DLL Autodetect ................................................... RO 5 Delay Compensation Counter Control 4-3 S2K Pad AC Coupling to VREF Signal in Address / Data Output Clock 2-0 S2K Pad Slew Rate Ctrl (7h is strongest) .... def=7h -39- Device 0 Register Descriptions KT133A - VT8363A ...
Page 46
... Device 0 Offset FD – Back-DoorControl 2 (00h) ........... RW 7-5 Reserved ........................................always reads 0 4-0 Max # of AGP Requests ........................... default = 0 00000 1 Request 00001 2 Requests 00010 3 Requests … … 11111 32 Requests (see also RxA7 and RxFC[1]) Device 0 Offset FF-FE – Back-Door Device ID (0000h) RW 15-0 Back-Door Device ID................................ default=00 -40- Device 0 Register Descriptions KT133A - VT8363A ...
Page 47
... Device 1 Offset 1-0 - Vendor ID (1106h) ..........................RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Device 1 Offset 3-2 - Device ID (8305h)............................RO 15-0 ID Code (reads 8305h to identify the VT8363A PCI- to-PCI Bridge device) Device 1 Offset 5-4 – Command (0007h) .........................RW 15-10 Reserved ........................................ always reads 0 9 Fast Back-to-Back Cycle Enable ...
Page 48
... I/O Limit registers (device 1 offset 1C-1D) .................................................... default 1 Do not forward I/O accesses to the AGP bus that are in the 100-3FFh address range even if they are in the range defined by the I/O Base and I/O Limit registers. ........................................always reads 0 1-0 Reserved -42- Device 1 Register Descriptions KT133A - VT8363A "Mono" text mode uses ...
Page 49
... I/O PCI PCI PCI 1 0 AGP AGP AGP PCI AGP PCI -43- KT133A - VT8363A Retry Status 0 No retry occurred................................... default 1 Retry Occurred ........................write 1 to clear Retry Timeout Action 0 No action taken except to record status ....... def 1 Flush buffer for write or return all 1s for read Retry Count 00 Retry 2, backoff CPU ...
Page 50
... Device 1 Register Descriptions KT133A - VT8363A CPU Write Cycles To Fast Write Cycle Alignment QW aligned, burstable DW aligned, nonburstable n/a DW aligned, non-burstable QW aligned, burstable n/a QW aligned, burstable DW aligned, non-burstable n/a QW aligned, burstable QW aligned, burstable QW aligned, non-burstable QW aligned, non-burstable ...
Page 51
... D3 Hot Device 1 Offset 85 – Power Mgmt Status (00h)............... RO 7-0 Power Mgmt Status ..................................default = 00 Device 1 Offset 86 – P2P Br. Support Extensions (00h 7-0 P2P Bridge Support Extensions................default = 00 Device 1 Offset 87 – Power Management Data (00h) ..... RO 7-0 Power Management Data.......................... default = 00 -45- Device 1 Register Descriptions KT133A - VT8363A ...
Page 52
... Output high voltage OH I Input leakage current IL I Tristate leakage current OZ Preliminary Revision 0.1, October 9, 2000 E S LECTRICAL PECIFICATIONS Min 0 -55 -0.5 = 3.1 - 3.6V) -0.5 CC Min Max -0.50 2 0.45 2.4 - +/-10 - +/-20 -46- KT133A - VT8363A Max Unit o C 110 o C 125 5.5 Volts V + 0.5 Volts CC Unit Condition 0 =4.0mA =-1.0mA OH uA 0<V < 0.45< ...
Page 53
... Power (VCCQ, VCCQQ) Case Temperature Drive strength for each output pin is programmable. See Rx6D for details. Preliminary Revision 0.1, October 9, 2000 Typ Max 3.5 Table 8. AC Timing Min / Max Conditions -47- KT133A - VT8363A Unit Condition mA Max operating frequency mA Max operating frequency mA Max operating frequency mA ...
Page 54
... Figure 5. Mechanical Specifications - 552-Pin Ball Grid Array Package Preliminary Revision 0.1, October 9, 2000 M S ECHANICAL PECIFICATIONS 35x35x2. -48- KT133A - VT8363A Y = Date Code Year W = Date Code Week R = Chip Revision L = Lot Code Mechanical Specifications ...