VT82C586B ETC-unknow, VT82C586B Datasheet
VT82C586B
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VT82C586B Summary of contents
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‹ 86$ 2IILFH 7DLSHL 2IILFH ...
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... Rx20[31:0] (moved to Rx48) I/O Base Address Register Power Management I/O(3040F and 3041 silicon) Rx40[6:5] (new) GPIO Direction Control Register • Electrical Spec Changes: Added PCI Cycle Timing • Mechanical Spec Changes: Added marking specs for 3040E/F, 3041 silicon -i- VT82C586B Initials Revision History ...
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... PCI Configuration Space Header .......................................................................................................................................................... 40 Power Management-Specific PCI Configuration Registers .................................................................................................................. 41 Power Management Subsystem Overview ............................................................................................................................................ 43 Power Management I/O-Space Registers .............................................................................................................................................. 46 ELECTRICAL SPECIFICATIONS............................................................................................................................................... BSOLUTE AXIMUM ATINGS DC C ................................................................................................................................................................ 55 HARACTERISTICS ...................................................................................................................................................... 56 IMING PECIFICATIONS PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 63 Revision 1.0 May 13, 1997 T C ABLE OF ONTENTS ................................................................................................................................................. 55 -ii- VT82C586B Table of Contents ...
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... FIGURE 1. PC SYSTEM CONFIGURATION USING THE VT82C586B ................................................................................. 3 FIGURE 2. PIN DIAGRAM............................................................................................................................................................. 4 FIGURE 3. STRAP OPTION CIRCUIT....................................................................................................................................... 31 FIGURE 4. POWER MANAGEMENT SUBSYSTEM BLOCK DIAGRAM ........................................................................... 43 FIGURE 5. ULTRADMA-33 IDE TIMING - DRIVE INITIATING DMA BURST FOR READ COMMAND.................... 58 FIGURE 6. ULTRADMA-33 IDE TIMING - DRIVE INITIATING BURST FOR WRITE COMMAND............................ 58 FIGURE 7 ...
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... TABLE 4. KEYBOARD CONTROLLER COMMAND CODES .............................................................................................. 23 TABLE 5. CMOS REGISTER SUMMARY................................................................................................................................. 26 TABLE 6. SCI/SMI/RESUME CONTROL FOR PM EVENTS................................................................................................. 44 TABLE 7. SUSPEND RESUME EVENTS AND CONDITIONS ............................................................................................... 44 TABLE 8. AC CHARACTERISTICS - PCI CYCLE TIMING.................................................................................................. 56 TABLE 9. AC CHARACTERISTICS - ULTRADMA-33 IDE BUS INTERFACE TIMING.................................................. 57 Revision 1.0 May 13, 1997 L T IST OF ABLES -iv- VT82C586B List of Tables ...
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... Bus master programming interface for SFF-8038i rev.1.0 and Windows-95 compliant Full scatter gather capability Support ATAPI compliant devices including DVD devices Support PCI native and ATA compatibility modes Complete software driver support Revision 1.0 May 13, 1997 VT82C586B PIPC P NTEGRATED ERIPHERAL PCI- OMPLIANT ...
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... Pin-compatible upgrade from VT82C586 and VT82C586A for existing designs Built-in Nand-tree pin scan test capability 0.5um mixed voltage, high speed and low power CMOS process Single chip 208 pin PQFP Revision 1.0 May 13, 1997 TM and plug and play BIOS compliant -2- VT82C586B Features ...
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... The IDE controller is SFF-8038i v1.0 and Microsoft Windows-95 compliant. b) Universal Serial Bus controller that is USB v1.0 and Universal HCI v1.1 compliant. The VT82C586B includes the root hub with two function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support ...
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... P INOUTS Figure 2. Pin Diagram 3&,,QWHJUDWHG 34)3 Note: Pin names in parentheses (...) indicate alternate function ‡ 3040 Rev F and Later Revisions † 3041 Rev A and Later Revisions -4- VT82C586B (IRQ8 ...
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... O Initialization. The VT82C586B asserts INIT if it detects a shut-down special cycle on the PCI bus soft reset is initiated by the register O Stop Clock. STPCLK# is asserted by the VT82C586B to the CPU in response to different Power-Management events. O System Management Interrupt. SMI# is asserted by the VT82C586B to the CPU in response to different Power-Management events. ...
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... Target Ready. Asserted when the target is ready for data transfer. B Stop. Asserted by the target to request the master to stop the current transaction. B Device Select. The VT82C586B asserts this signal to claim PCI transactions through positive or subtractive decoding. B Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#. ...
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... ISA data bus. O Bus Address Latch Enable. BALE is an active high signal asserted by the VT82C586B to indicate that the address (SA[19:0], LA[23:17] and the SBHE# signal) is valid I 16-Bit I/O Chip Select. This signal is driven by I/O devices on the ISA Bus to indicate that they support 16-bit I/O bus cycles ...
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... DMA Request. The DRQ lines are used to request DMA services from the VT82C586B’s DMA controller. O Acknowledge. The DACK# output lines indicate a request for DMA service has been granted. O Terminal Count. The VT82C586B asserts TC to DMA slaves as a terminal count indicator. I ISA Master Request. (see below pin 137) B Multifunction Pin Normal Operation: Speaker Drive ...
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... SDDIR. This pin may be programmed to serve as a direction control for the IDE interface transceivers (see SOE#) separate from MASTER#. This function was introduced in revision A of the 3041 silicon and not available in earlier chips. Rx48[5] Rx59[2] Pin Function 0 0 MASTER# (input MIRQ2 (input -illegal SDDIR (output) -9- VT82C586B Pinouts ...
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... SA[15-0] connected to the “B” side. I Device DMA Request A. Primary channel DMA request I Device DMA Request B. Secondary channel DMA request O Device DMA Acknowledge A. Primary channel DMA acknowledge O Device DMA Acknowledge B. Secondary channel DMA acknowledge -10- VT82C586B Pinouts ...
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... GPIO4 Configuration bit low: Write Enable for General Purpose Outputs: Connects to the latch enable (LE pin) of the external 373 latches whose data pins connect to SD15-8 and XD7-0 for GPO15-0. -11- VT82C586B 2 C pair (by software convention this pin pair (by software convention this pin is ...
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... External RTC - IRQ8# input on pin 106 1 x Internal RTC - IRQ8# input not required O Multifunction Pin Internal RTC enabled: RTC Crystal Output: 32.768Khz crystal output Internal RTC disabled: External RTC Chip Select I RTC Battery. Battery input for internal RTC -12- VT82C586B Pinouts ...
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... Signal Description I Power Good. Connected to the POWERGOOD signal on the Power Supply. O PCI Reset. An active low reset signal for the PCI bus. The VT82C586B will generate PCIRST# during power-up or from the control register. O Reset Drive. RSTDRV is the reset signal to the ISA bus. ...
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... R EGISTERS Register Overview The following tables summarize the configuration and I/O registers of the VT82C586B. These tables also document the power-on default value (“Default”) and access type (“Acc”) for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), “—” for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1’ ...
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... Default Acc D2 Write Request RW D4 Write Single Mask D6 Write Mode D8 Clear Byte Pointer FF Default Acc — Master Clear — Clear Mask — Read / Write Mask — RW -15- VT82C586B Default Acc Register Overview ...
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... Subsystem ID Write 71-7F -reserved- Default Acc — — 0300 RW -16- VT82C586B Default Acc — † — Default Acc 0000 RW 0000 RW 0000 RW ...
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... Primary Channel Command -reserved Primary Channel Status 3 -reserved- 4-7 Primary Channel PRD Table Addr 8 Secondary Channel Command 9 -reserved- A Secondary Channel Status B -reserved- C-F Secondary Channel PRD Table Addr -17- VT82C586B Default Acc A8A8A8A8 ...
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... Port 2 Status / Control — 00000301 RW 00 — — Default Acc — — 2000 RW 00 — -18- VT82C586B Default Acc 0000 RW 0000 WC 0000 RW 0000 RW 00000000 0080 WC 0080 WC Register Overview ...
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... RW 43-42 GPIO Port Output Value 00 — 45-44 GPIO Port Input Value 00 WO 47-46 GPO Port Output Value 00 WO 49-48 GPI Port Input Value 00 WO FF-4A -reserved- 00 — -19- VT82C586B Default Acc 0000 WC 0000 RW 0000 RW 00 — 0000 0000 RW 00 — Default Acc 0000 0000 RW 00 ...
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... Register Number Used to select a specific DWORD in the device’s configuration space 1-0 Fixed ........................................ always reads 0 Port CFF-CFC - Configuration Data .............................. RW Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers. Revision 1.0 May 13, 1997 -20- VT82C586B Configuration Space I/O ...
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... Enable Timer/Counter 2 Revision 1.0 May 13, 1997 Port 92h - System Control ................................................ RW 7-6 5 (duplication of that -21- VT82C586B Hard Disk Activity LED Status 0 Off .................................................... default 1-3 On Reserved ........................................ always reads 0 Power-On Password Bytes Inaccessable ..default=0 Reserved ........................................ always reads 0 A20 Address Line Enable 0 A20 disabled / forced 0 (real mode) ...... default ...
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... System Flag ................................................ default=0 – – This bit may be read back as status register bit-2 1 Mouse Interrupt Enable 0 Keyboard Interrupt Enable -22- VT82C586B 0 Keyboard Output Buffer Empty............. default 1 Keyboard Output Buffer Full 0 Input Buffer Empty................................ default 1 Input Buffer Full 0 Power-On Default .................................. default 1 ...
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... Port 64 - Keyboard / Mouse Command .......................... WO This port is used to send commands to the keyboard / mouse controller. The command codes recognized by the VT82C586B are listed n the table below. Note: The VT82C586B Keyboard Controller is compatible with the VIA VT82C42 Industry-Standard Controller except that due to its integrated nature, many of the ...
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... Channel 3 DMA Page (M-3).........RW 0000 0000 1000 1111 Channel 4 DMA Page (S-0) ..........RW 0000 0000 1000 1011 Channel 5 DMA Page (S-1) ..........RW 0000 0000 1000 1001 Channel 6 DMA Page (S-2) ..........RW 0000 0000 1000 1010 Channel 7 DMA Page (S-3) .........RW -24- VT82C586B ...
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... Note that not all bits of the address are decoded. The Timer / Counters are compatible with the Intel 8254 Timer / Counter chip. Detailed descriptions of 8254 Timer / Counter operation can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications. -25- VT82C586B Register Descriptions ...
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... Date Alarm control registers are 7E Month Alarm 7F Century Field 80-FF Software-Defined Storage Registers (128 Bytes) For reference, the Table 5. CMOS Register Summary -26- VT82C586B Binary Range BCD Range 00-3Bh 00-3Bh 00-3Bh 00-3Bh am 12hr: 01-1Ch pm 12hr: 81-8Ch 24hr: 00-17h am 12hr: 01-1Ch pm 12hr: 81-8Ch 24hr: 00-17h ...
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... Offset 8 - Revision ................................................ RO 7-0 ID for VT82C586 = 0xh ID for VT82C586A = 2xh ID for VT82C586B = 3xh (3040 OEM Silicon) ID for VT82C586B = 4xh (3041 Production Sil.) Offset 9 - Program Interface = 00h ................................... RO Offset A - Sub Class Code = 01h ....................................... RO Offset B - Class Code = 06h ............................................... RO Offset E - Header Type = 80h ............................................ RO 7-0 Header Type Code ...
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... Note: Always mask this bit. This bit may read back as either but must always be programmed with 0. 2 Write Delay Transaction Time-Out Timer Enable 0 Disable................................................... default 1 Enable 1 Read Delay Transaction Time-Out Timer Enable 0 Disable................................................... default 1 Enable Software PCI Reset ......write 1 to generate PCI reset 0 -28- VT82C586B Register Descriptions ...
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... Forward DC000-DFFFF Accesses to PCI ......def=0 6 Forward D8000-DBFFF Accesses to PCI ......def=0 5 Forward D4000-D7FFF Accesses to PCI .......def=0 4 Forward D0000-D3FFF Accesses to PCI .......def=0 3 Forward CC000-CFFFF Accesses to PCI .....def=0 2 Forward C8000-CBFFF Accesses to PCI ......def=0 1 Forward C4000-C7FFF Accesses to PCI .......def=0 0 Forward C0000-C3FFF Accesses to PCI .......def=0 -29- VT82C586B Register Descriptions ...
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... Enable POS Status output on pin 90. Alternate functions of pin 90 are APICCS# and MIRQ0 if this bit is not set (see bit-0 below). 2 MIRQ2 / MASTER# Selection (Pin 137) 0 MIRQ2................................................... default 1 MASTER# 1 MIRQ1 / KEYLOCK Selection (Pin 106) 0 MIRQ1................................................... default 1 KEYLOCK 0 MIRQ0 / APICCS# Selection (Pin 90) 0 MIRQ0................................................... default 1 APICCS# -30- VT82C586B Register Descriptions ...
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... RTC SRAM should be accessed at either ports 70/71 or 72/73. RTC Test Mode Enable (do not program) .default=0 0 Offset 5C - DMA Control (3041 Silicon Only) ............... RW ........................................ always reads 0 7-1 Reserved 0 DMA Line Buffer Disable 0 DMA cycles can be to/from line buffer ....... def 1 Disable DMA Line Buffer -31- VT82C586B If the internal RTC is Register Descriptions ...
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... Offset 6F-6E - Distributed DMA Ch 7 Base / Enable ..... RW 15-4 Channel 7 Base Address Bits 15-4 .......... default = 0 3 Channel 7 Enable 0 Disable ...................................................default 1 Enable 2-0 Reserved ........................................ always reads 0 Revision 1.0 May 13, 1997 Miscellaneous Offset 73-70 - Subsystem ID (3041 Silicon Only) ........... WO 31-0 Subsystem ID and Subsystem Vendor ID Write Only. Always reads back 0. Contents may be read at offset 2C. -32- VT82C586B Register Descriptions ...
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... PCI configuration registers and Bus Master IDE I/O registers. The PCI configuration registers are located in the function 1 PCI configuration space of the VT82C586B. The Bus Master IDE I/O registers are defined in the SFF8038i v1.0 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID (1106h=VIA) ................................ RO Offset 3-2 - Device ID (0571h=IDE Controller) ...
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... Port Address ....................................... default=CC0h 3-0 Fixed at 0001b .................................................. fixed Revision 1.0 May 13, 1997 Offset 3C - Interrupt Line (0Eh) ..................................... RW Offset 3D - Interrupt Pin (00h) ......................................... RO 7-0 Interrupt Routing Mode 00h Legacy mode interrupt routing............... default 01h Native mode interrupt routing Offset 3E - Min Gnt (00h) ................................................. RO Offset 3F - Max Latency (00h).......................................... RO -34- VT82C586B Register Descriptions ...
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... Default=0 (disabled) 3-2 Reserved ........................................ always reads 0 1-0 Max DRDY Pulse Width Maximum DRDY# pulse width after the cycle count. Command will deassert in spite of DRDY# status to avoid system ready hang limitation.......................................... default 01 64 PCI clocks 10 128 PCI clocks 11 192 PCI clocks -35- VT82C586B Register Descriptions ...
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... Each byte defines UltraDMA33 operation for the indicated drive. The bit definitions are the same within each byte. Offset 61-60 - Primary Sector Size .................................. RW 15-12 Reserved ........................................ always reads 0 11-0 Number of Bytes Per Sector ................ default=200h Offset 69-68 - Secondary Sector Size .............................. RW 15-12 Reserved ........................................ always reads 0 11-0 Number of Bytes Per Sector ................ default=200h -36- VT82C586B Register Descriptions ...
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... Refer to the SFF 8038I v1.0 specification for further details. Offset 0 - Primary Channel Command Offset 2 - Primary Channel Status Offset 4-7 - Primary Channel PRD Table Address Offset 8 - Secondary Channel Command Offset A - Secondary Channel Status Offset C-F - Secondary Channel PRD Table Address Revision 1.0 May 13, 1997 -37- VT82C586B Register Descriptions ...
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... There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the function 2 PCI configuration space of the VT82C586B. The USB I/O registers are defined in the UHCI v1.1 specification. PCI Configuration Space Header Offset 1-0 - Vendor ID ....................................................... RO 0-7 Vendor ID ...
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... Refer to the UHCI v1.1 specification for further details. Offset 1-0 - USB Command Offset 3-2 - USB Status Offset 5-4 - USB Interrupt Enable Offset 7-6 - Frame Number Offset B-8 - Frame List Base Address Offset 0C - Start Of Frame Modify Offset 11-10 - Port 1 Status / Control Offset 13-12 - Port 2 Status / Control Offset 1F-14 - Reserved -39- VT82C586B Register Descriptions ...
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... Power Management Registers (Function 3) This section describes the ACPI (Advanced Configuration and Power Interface) Power Management VT82C586B. This system supports both ACPI and legacy power management functions and is compatible with the APM v1.2 and ACPI v0.9 specifications. PCI Configuration Space Header Offset 1-0 - Vendor ID ....................................................... RO 0-7 Vendor ID ...
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... The definitions of the registers in the Power Management I/O Register Block are included later in this document, following the Power-Management-Specific PCI Configuration register descriptions and the Power Management Subsystem overview. 7-0 00000001b -41- VT82C586B Register Descriptions ...
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... Code) may be changed by writing the desired value to this location. Register (Power Offset 63 - Base Class Read Value ................................... WO 7-0 Rx0B Read Value The value returned by the register at offset 0Bh (Base Class Code) may be changed by writing the desired value to this location. -42- VT82C586B Timer Reload Enable Register Register Descriptions (Power ...
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... Sixteen GPI and sixteen GPO pins using external buffers (244 buffers for input and 373 latches for output). Pins 87, 88 and 94 of the VT82C586B are dedicated general purpose I/O pins that can be used as inputs, outputs or I/O with external SMI capability. In particular, pins 87 and 88 can be used to implement a software-implemented I configuration and general purpose peripheral communication ...
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... In either suspend state, there is minimal interface between powered and non-powered planes. Revision 1.0 May 13, 1997 The VT82C586B allows the following events to wake up the system from the two suspend states and from the C2 state to the normal working state (processor in C0 state): • Activation of External Inputs: PWRBTN#, RI#, GPIO0 and other EXTSMI pins (see table below) • ...
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... Peripheral Events Primary and secondary events define system events in general and the response is typically expressed in terms of system events. Individual peripheral events can also be monitored by the VT82C586B through the GP1 timer. The following four categories of peripheral events are distinguished (via register GP_RLD_EN): Bit-7 ...
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... VT82C586B ........................................ always reads 0 Reserved ........................................ always reads 0 Reserved ........................................ always reads 0 RTC Enable (RTC_EN)............................default = 0 This bit may be set to trigger either an SCI or an SMI (depending on the setting of the SCI_EN bit generated when the RTC_STS bit is set. ...
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... S0 (working) system state. The timer is reset to an initial value of zero during a reset, and then continues counting until the 14.31818 MHz input to the chip is stopped. If the clock is restarted without a reset, then the counter will continue counting from where it stopped. -47- VT82C586B Register Descriptions ...
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... Enable bit (Function 3 Rx10 bit-4) is set. 3041 Silicon: Reads from this register put the processor into the Stop Clock state (the VT82C586B asserts STPCLK# to suspend the processor). Wake up from Stop Clock state is by interrupt (INTR, SMI, PWRBTN#, RTC wakeup, or pin toggle SCI). ...
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... VDD_5V power plane by setting PWRON = 1). 7-1 Reserved ........................................ always reads 0 0 EXTSMI0 Toggle PS Control (E0_PS_CTL) def=0 This bit enables the setting of the EXT0_STS bit to resume the system from suspend (turn on the VDD_5V power plane by setting PWRON = 1). -49- VT82C586B Register Descriptions ...
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... Secondary Event Timer Time Out Enable (STTO_EN) ......................................................def=0 This bit may be set to trigger an SMI to be generated when the STTO_STS bit is set. 0 Primary Activity Enable (PACT_EN) ............def=0 This bit may be set to trigger an SMI to be generated when the PACT_STS bit is set. -50- VT82C586B ........................................ always reads 0 Register Descriptions ...
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... Revision 1.0 May 13, 1997 Offset 2F - SMI Command (SMI_CMD) ............. 3041: RW ............... 3040: WO, always reads 0 (Read at Func 3 Rx47) 7-0 SMI Command Writing to this port sets the SW_SMI_STS bit. Note that if the SW_SMI_EN bit is set (see bit-6 of the Global Enable register at offset 2Ah), then an SMI is generated. -51- VT82C586B Register Descriptions ...
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... Enable GP0 Timer Reload on Primary Activity 1 = setting of PACT_STS causes GP0 timer to reload. Primary activities are enabled via the Primary Activity Detect Enable register (offset 37-34) with status recorded in the Primary Activity Detect Status register (offset 33-30). -52- VT82C586B Register Descriptions ...
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... GPIO3_CFG=0: EXTSMI3# on XD3 (pin 117) GPIO3_CFG=1: EXTSMI3# on GPIO3 (pin 92) 2 EXTSMI2# Input Value (on GPIO2 pin 88) 1 EXTSMI1# Input Value (on GPIO1 pin 87) 0 EXTSMI0# Input Value (on GPIO0 pin 94) Note: GPIO3_CFG and GPIO4_CFG are located in PCI Configuration Register function 3 offset 40h. -53- VT82C586B ........................................ always reads 0 Register Descriptions ...
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... GPIO3_CFG bit is zero to define pin 92 as This port is GPI_RE#. 7-0 GPI7-0 Value. Input port value for the external GPI port connected to XD7-0. This port is available only if the GPIO3_CFG bit is zero to define pin 92 as GPI_RE#. GPIO3_CFG is in PCI Config Register function 3 offset 40h. -54- VT82C586B Register Descriptions ...
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... Tristate leakage current OZ I Power supply current CC Revision 1.0 May 13, 1997 E S LECTRICAL PECIFICATIONS Min 0 -55 -0.5 = 5V) -0 3.1 - 3.6V) -0.5 DD Min Max -0.50 2 2.4 - +/-10 - +/-20 - -55- Max Unit 125 5.5 Volts 5.5 Volts V + 0.5 Volts DD Unit Condition 0.8 V +0 =4.0mA =-1.0mA OH uA 0<V < 0.45<V <V OUT Electrical Specifications VT82C586B ...
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... PREQ# Valid Delay from PCLK Rising VD T FRAME#,TRDY#,IRDY# Float Delay from PCLK Rising FD T CBE[3:0]#, STOP#,DEVSEL# Float Delay from PCLK Rising FD Revision 1.0 May 13, 1997 Table 8. AC Characteristics - PCI Cycle Timing Parameter -56- VT82C586B Min Max Unit Notes ...
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... Delay time of PCLK to DIOR Data setup time during PIO write WDS T Data hold time during PIO write WDH T Data setup time during PIO read RDS T Data hold time during PIO read RDH Revision 1.0 May 13, 1997 -57- VT82C586B Timing Unit 29.3 ns 1.1 ns 2.3 ns 29.3 ns 42.2 ns 17 ...
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... DDRQ (Drive) DDACK# (Host) STOP (Host) DDMARDY# (Drive) HSTROBE (Host) DDMARDY# (Drive) HSTROBE (Host) Data Figure 6. UltraDMA-33 IDE Timing - Drive Initiating Burst for Write Command Revision 1.0 May 13, 1997 ENV1 LI1 T DS1 T DH1 ENV2 -58- VT82C586B DVH2 T DVS2 Electrical Specifications ...
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... DDRQ (Drive) DDACK# (Host) For Write: DDMARDY# (Drive) HSTROBE (Host) For Read: STOP (Host) HDMARDY# (Host) Figure 7. UltraDMA-33 IDE Timing - Pausing a DMA Burst Revision 1.0 May 13, 1997 T RFS T RP -59- VT82C586B Electrical Specifications ...
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... Figure 8. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Read Command DDRQ (Drive) DDACK# (Host) STOP (Host) DDMARDY# (Host) HSTROBE (Host) Data Figure 9. UltraDMA-33 IDE Timing - Drive Terminating DMA Burst During Write Command Revision 1.0 May 13, 1997 T LI4 CRC T T DVS4 ZA4 T LI5A T MLI5 T LI5B CRC T DVS5 -60- VT82C586B T DVH4 T DVH5 Electrical Specifications ...
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... Figure 10. UltraDMA-33 IDE Timing - Host Terminating DMA Burst During Read Command DDRQ (Drive) DDACK# (Host) STOP (Host) HSTROBE# (Host) Data Figure 11. UltraDMA-33 IDE Timing - Host Terminating DMA Burst During Write Command Revision 1.0 May 13, 1997 T MLI6 T ZA6 CRC T MIL7 T LI7 T T DVS7 CRC -61- VT82C586B DVH7 Electrical Specifications ...
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... T 2 DCS3# / DCS1# DA [2: DIOW# DD Write DIOR# DD Read Figure 12. UltraDMA-33 IDE Timing - PIO Cycle Revision 1.0 May 13, 1997 WDS WDH RDH RDS -62- VT82C586B Electrical Specifications ...
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... P ACKAGE 7<3 7<3 Figure 13. Mechanical Specifications - 208-Pin Plastic Flat Package Revision 1.0 May 13, 1997 M S ECHANICAL 4 -63- PECIFICATIONS Y = Date Code Year W = Date Code Week V = Chip Version CD = OEM Version CE = Production Version R = Revision Code L = Lot Code Package Mechanical Specifications VT82C586B ...