MK2049-01SI ETC-unknow, MK2049-01SI Datasheet

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MK2049-01SI

Manufacturer Part Number
MK2049-01SI
Description
Manufacturer
ETC-unknow
Datasheet
MDS 2049-01 J
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com
Reference
Crystal
The MK2049 is a Phase-Locked Loop (PLL) based
clock synthesizer, which accepts an 8 kHz clock
input as a reference and generates T1, E1, T3, E3,
and OC3 frequencies. The device can also accept a
T1, E1, T3, or E3 input clock and provide the
same output for loop timing. All outputs are
frequency locked together and to the input. This
allows for the generation of locked clocks to an
8 kHz backplane clock, simplifying clock
distribution in communications systems.
MicroClock can customize this device for many
other different frequencies. Contact your
MicroClock representative for more details.
For a fixed input-output phase relationship, refer
to the MK2049-02, -03, or -3x. The MK2049-3x
are 3.3 V devices.
Description
Block Diagram
Clock
FS3:0
Input
4
X1
X2
Oscillator
Crystal
VDD GND
4
External/
Timing
Loop
Mux
4
1
CAP1
Features
• Packaged in 20 pin SOIC
• Meets the TR62411, ETS300 011, and GR-1244
• Accepts multiple inputs: 8 kHz backplane clock or
• Locks to 8 kHz ±100 ppm (External mode)
• Exact internal ratios eliminate the need for external
• Zero ppm synthesis error in all output clocks.
• Output clock rates include T1, E1, T3, E3, and
• 5 V ±5% operation
• Offered in Commercial and Industrial temperature
versions
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
Loop Timing frequencies
dividers
OC3÷8
Control, and
Attenuation
Synthesis,
Circuitry
Communications Clock PLL
Clock
Jitter
PLL
CAP2
Output
Output
Output
Buffer
Buffer
Buffer
MK2049-01
Revision 040601
CLK1
CLK2
8 kHz

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MK2049-01SI Summary of contents

Page 1

... Description The MK2049 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference and generates T1, E1, T3, E3, and OC3 frequencies. The device can also accept a T1, E1, T3 input clock and provide the same output for loop timing. All outputs are frequency locked together and to the input ...

Page 2

... CAP2. resistor in series between this pin and CAP1. MK2049-01 CLK2 Crystal 3.088 12.288 4.096 12.288 44.736 12.288 34.368 12.288 38.88 12.96 CLK2 Crystal 3.088 12.288 4.096 12.288 44 ...

Page 3

... Absolute Maximums may affect device reliability. MDS 2049-01 J Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com Communications Clock PLL Conditions Minimum Referenced to GND -0.5 0 MK2049-01SI only -40 Max of 10 seconds -65 4.75 2 IOH=-4mA VDD-0.4 IOH=-25mA 2 ...

Page 4

... OPERATING MODES The MK2049-01 has two operating modes: External and Loop Timing. Although both modes use an input clock to generate various output clocks, there are important differences in their input requirements. External Mode The MK2049-01 accepts an external 8 kHz clock and will produce a number of common communication clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle ...

Page 5

... The typical telecom reference frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature, and aging ...

Page 6

... The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal. External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should use short traces between the MK2049 and the crystal ...

Page 7

... Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com Communications Clock PLL Minimum Typical Maximum - -20 20 Note 1 7 none none 250 35 7 MK2049-01 Units °C ppm ppm ppm ppm pF pF none Ohms Revision 040601 ...

Page 8

... determine the value of the crystal capacitors: 1. Connect VDD of the MK2049 to 5.0 V. Connect pin 18 of the MK2049 to the second power supply. Adjust the voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK1 or CLK2 output . 2. Adjust the voltage on pin 18 to 3.0 V. Measure and record the frequency of the same output. ...

Page 9

... Measured Jitter Output (UIp-p) Measured Jitter Output (UIp-p) Input Jitter Output Jitter Magnitude Magnitude (UIp-p) (UIp-p) 10.5 0.071 10.5 0.07 10.5 0.144 10.5 0.12 10.5 0.08 10.5 0.07 10.5 0.066 10.5 0.065 10.5 0.06 10.5 0.06 10.5 0.058 10.5 0.06 10.5 0.062 9 MK2049-01 Communications Clock PLL Jitter Attenuation (dB) 19.41 25.04 28.87 36.65 48.64 55.92 60.00 60.00 60.00 60.00 57.79 52.00 44.81 Jitter Attenuation (dB) 43.4 43.52 37.26 38.84 42.36 43.52 44.03 44.17 44.86 44.86 45.16 44.86 44.58 Revision 040601 ...

Page 10

... Measured Jitter Output (UIp-p) Measured Jitter Output (UIp-p) Input Jitter Output Jitter Magnitude Magnitude (UIp-p) (UIp-p) 1.5 0.113 1.5 0.094 1.5 0.077 1.5 0.069 1.5 0.07 0.72 0.068 0.36 0.007 0.24 0.007 0.2 0.007 0.2 0.007 0.2 0.007 0.2 0.007 10 MK2049-01 Communications Clock PLL Jitter Attenuation (dB) 38.42 40.60 43.52 43.52 46.62 47.96 47.96 41.58 35.56 32.04 30.46 30.46 30.46 Jitter Attenuation (dB) 22.46 24.06 25.79 26.74 26.62 20.5 34.22 30.7 29.12 29.12 29.12 29.12 Revision 040601 ...

Page 11

... MDS 2049-01 J Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel •www.icst.com 45° Marking MK2049-01S MK2049-01S MK2049-01SI MK2049-01SI 11 MK2049-01 Communications Clock PLL 20 pin SOIC Inches Inches Millimeters Millimeters Symbol Min Max ...

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