A10V20B-VQ80C

Manufacturer Part NumberA10V20B-VQ80C
Description357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
ManufacturerActel
A10V20B-VQ80C datasheet
 


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ACT
1 Series FPGAs
F e a t u re s
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
®
• Replaces up to twenty 20-Pin PAL
Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
D e s c r ip t i on
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
®
PLICE
antifuse technology. The unique architecture offers
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
clock driver with a hardwired distribution network. The
network provides efficient clock distribution with minimum
skew.
The user-definable I/Os are capable of driving at both TTL
and CMOS drive levels. Available packages include plastic
and ceramic J-leaded chip carriers, ceramic and plastic quad
flatpacks, and ceramic pin grid array.
Apr i l 199 6
© 1996 Actel Corporation
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Pr o d u c t F a m i ly P r o fi l e
A1010B
Device
A10V10B
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Logic Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
112,000
User I/Os (maximum)
Packages:
44 PLCC
68 PLCC
100 PQFP
80 VQFP
84 CPGA
Performance
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
Note:
See Product Plan on page 1-286 for package availability.
Th e D e s i g n e r a n d D e s ig n e r
A d v a n t a g e ™ Sy s t e ms
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
®
Microsoft
Windows
and X Windows
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmap
VHDL optimization and synthesis tool
and the ACTgen
Macro Builder, a powerful macro function
generator for counters, adders, and other structural blocks.
A1020B
A10V20B
1,200
2,000
3,000
6,000
30
50
12
20
295
547
147
273
22
22
13
13
186,000
57
69
44 PLCC
68 PLCC
84 PLCC
100 PQFP
80 VQFP
84 CPGA
84 CQFP
75 MHz
75 MHz
55 MHz
55 MHz
graphical user
1-283

A10V20B-VQ80C Summary of contents