A1020B-PL68C Actel, A1020B-PL68C Datasheet

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A1020B-PL68C

Manufacturer Part Number
A1020B-PL68C
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
Actel
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RadTolerant FPGAs
Features
General Characteristics
High Density and Performance
Product Family Profile
Table 1 •
October 2004
© 2004 Actel Corporation
Device
Capacity
Logic Modules
User I/Os (Maximum)
Performance
Packages (by Pin Count)
System Gates
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
S-Modules
C-Modules
System Speed (Maximum)
CQFP
• Tested Total Ionizing Dose (TID) Survivability Level
• No Single Event Latch-Up Below a Minimum LET
• Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and
• Offered as Class B and E-Flow (Actel Space Level
• QML Certified Devices
• 100% Military Temperature Tested (–55°C to
• 4,000 to 20,000 Logic Equivalent Gates
• 2,000 to 10,000 ASIC Equivalent Gates
• Up to 85 MHz Internal Performance
(Linear Energy Transfer) Threshold of 80 MeV-cm
for All RT (RadTolerant) Devices
256-Pin Ceramic Quad Flat Pack
Flow)
+125°C)
RadTolerant Family
RT1020
20 MHz
6,000
4,000
2,000
5,000
547
N/A
547
50
20
69
84
2
/mg
RT1280A
40 MHz
24,000
16,000
20,000
8.000
1,232
200
624
608
140
172
80
Easy Logic Integration
• Up to 60 MHz System Performance
• Up to 228 User I/Os
• Up to Four Fast, Low-Skew Clock Networks
• Nonvolatile, User Programmable
• Pin-Compatible Commercial Devices Available for
• Highly
• 100% Resource Utilization with 100% Pin-Locking
• Secure Programming Technology Prevents Reverse
• Permanently Programmed
• Unique In-System Diagnostic and Verification
Prototyping
Automatic Place-and-Route
Engineering and Design Theft
Power-Up
Capability with Silicon Explorer
RT1425A
60 MHz
7,500
5,000
2,500
6,250
132
310
160
150
100
60
25
Predictable
See Actel’s website for the latest version of the datasheet
RT1460A
60 MHz
18,000
12,000
15.000
6,000
196
150
848
432
416
168
60
Performance
for
RT14100A
60 MHz
30,000
20,000
10,000
25,000
1,377
Operation on
256
250
100
697
680
228
with
v 3 . 1
100%
i

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A1020B-PL68C Summary of contents

Page 1

... Energy Transfer) Threshold of 80 MeV-cm for All RT (RadTolerant) Devices • Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and 256-Pin Ceramic Quad Flat Pack • Offered as Class B and E-Flow (Actel Space Level Flow) • QML Certified Devices • 100% Military Temperature Tested (–55°C to +125° ...

Page 2

... RT1460A = 12,000 Gates—RadTolerant ACT 3 RT14100A = 20,000 Gates—RadTolerant ACT 3 A1020B A1280A A1425A A1460A A14100A = 20,000 Gates—ACT 3 Device Resources FPGA Device Type Logic Modules RT1020/A1020B 547 RT1280A/A1280A 1,232 RT1425A/A1425A 310 RT1460A/A1460A 848 RT14100A/A14100A 1,377 Note: Package Definition: CQFP = Ceramic Quad Flat Pack Contact your Actel sales representative for product availability ...

Page 3

... Product Plan ACT 1 RT1020 Device 84-Pin Ceramic Quad Flat Pack (CQFP) A1020B Device (Prototyping Use) 84-Pin Ceramic Quad Flat Pack (CQFP) ACT 2 RT1280A Device 172-Pin Ceramic Quad Flat Pack (CQFP) A1280A Device (Prototyping Use) 172-Pin Ceramic Quad Flat Pack (CQFP) ACT 3 ...

Page 4

... Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 RT1020, A1020B Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 RT1280A, A1280A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 RT1425A, A1425A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 RT1460A, A1460A Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 RT14100A, A14100A Timing Characteristics ...

Page 5

... Device Description The RT1020 device contains the same architecture as the A1020, A1020A, and A1020B devices. The architecture, a combinatorial logic module logic structure with 8 inputs and 1 output. The logic itself is comprised of a 4-input MUX, ...

Page 6

... I/O modules, which are the building blocks for fast logic designs. Logic Modules These RadTolerant devices contain two types of logic modules, combinatorial (C-modules) and sequential (S-modules). RT1020 and A1020B devices contain only C- modules. The C-module, shown !S1*!S0*D00+!S1*S0*D01+S1*!S0*D10+S1*S0*D11 where: ...

Page 7

The S-module, shown in Figure implement high-speed sequential functions within a single logic module. The S-module implements the same combinatorial logic function as the C-module while adding a sequential element. The sequential element can be configured as either a D-type ...

Page 8

... The RadTolerant devices contain flexible I/O structures in that each output pin has a dedicated output enable control. The I/O module can be used to latch input and/or output data, providing a fast setup time. In addition, the Actel Designer software tools can build a D-flip-flop, using a C-module, to register input and/or output signals The Actel Designer software development tools provide a design library of I/O macros ...

Page 9

... In accordance with applicable Actel device specification 1015, Condition D, 160 hours @ 125° hours @ 150°C In accordance with applicable Actel device specification 5% In accordance with applicable Actel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 2009 v3 ...

Page 10

... External Visual Notes: 1. Actel offers the extended flow for customers that require additional screening beyond the requirements of MIL-STD-883, Class B. Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The exceptions to Method 5004 are shown in notes 2 and 3 below. 2. Wafer lot acceptance is performed to Method 5007 ...

Page 11

... Supply Current CC( Dynamic V Supply Current CC(D) CC Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time min Not tested; for information only 0V MHz OUT Parameter ...

Page 12

... Static Power Component Actel FPGAs have small static power components that result in power dissipation lower than that of PALs or PLDs. By integrating multiple PALs or PLDs into one FPGA, an even greater reduction in board-level power + dissipation can be achieved. The power due to standby current is typically a small EQ 1-3 component of the overall power ...

Page 13

... Equivalent capacitance is calculated by measuring specified frequency and voltage for each circuit component of interest. Measurements are made over a range of frequencies at a fixed value of V capacitance is frequency-independent, so the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown in RT1020, RT1280A, A1020B A1280A 3.7 5.8 22.1 12.9 32.1 23 ...

Page 14

... Number of clock loads on the first routed array 1 clock q = Number of clock loads on the second routed array 2 clock (not applicable for RT1020 or A1020B Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock 2 (not applicable for RT1020 or A1020B) ...

Page 15

... To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The guidelines below are meant to represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation. RT1020, A1020B, RT1280A, A1280A Logic Modules (m) Input Switching (n) ...

Page 16

... RadTolerant FPGAs Input Delay I/O Module t INYL = 3.9 ns ARRAY CLOCK t CKH = 6 MAX = 55 MHz Figure 1-6 • RT1020, A1020B Timing Model Input Delays I/O Module t INYL = 3 INH = 2 INSU = 3 INGL = 6.6 ns ARRAY CLOCKS t CKH = 13 MAX = 73 MHz Notes: 1. *Values shown for RT1280A –1 at worst-case military conditions. ...

Page 17

Input Delays I/O Module t IRD2 = 1 INY = 4 INH = 0 INSU = 2 ICKY = 7.0 ns ARRAY CLOCK t HCKH = 5 HMAX ...

Page 18

RadTolerant FPGAs Parameter Measurement V CC GND In 50% 50 1.5V PAD 1. DLH t DHL Figure 1-9 • Output Buffer Delays Load 1 (Used to measure propagation delay) To the Output under Test Figure ...

Page 19

Sequential Timing Characteristics SUD G, CLK E Q PRE, CLR D represents all data functions involving A, B, and S for multiplexed flip-flops. Figure 1-13 • Flip-Flops and Latches (RT1280A, A1280A SUD G, CLK ...

Page 20

RadTolerant FPGAs CLK PAD Figure 1-15 • Input Buffer Latches (R1280A, A1280A Figure 1-16 • Output Buffer Latches (RT1280A, A1280A PAD IBDL G CLKBUF PAD G t INSU t HEXT CLK t SUEXT D PAD ...

Page 21

... RT1020, A1020B Timing Characteristics Table 1-10 • RT1020, A1020B Logic and Input Modules Worst-Case Military Conditions, V Parameter Logic Module Propagation Delays t Single Module PD1 t Dual Module Macros PD2 t Sequential Clock Latch Flip-Flop (Latch) Reset Logic Module Predicted Routing Delays ...

Page 22

... RadTolerant FPGAs Table 1-11 • RT1020, A1020B Output Module Worst-Case Military Conditions, V Parameter Global Clock Network t Input Low to High CKH t Input High to Low CKL t Minimum Pulse Width High PWH t Minimum Pulse Width Low PWL t Maximum Skew CKSW t Minimum Period P f Maximum Frequency ...

Page 23

RT1280A, A1280A Timing Characteristics Table 1-12 • RT1280A, A1280A Logic Module Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Single Module PD1 t Sequential Clock-to Latch G-to Flip-Flop (Latch) Reset-to-Q RS Logic Module ...

Page 24

RadTolerant FPGAs Table 1-13 • RT1280A, A1280A Input Module Worst-Case Military Conditions, V Parameter Description Input Module Propagation Delays t Pad-to-Y HIGH INYH t Pad-to-Y LOW INYL t G-to-Y HIGH INGH t G-to-Y LOW INGL Input Module Predicted Routing Delays ...

Page 25

Table 1-14 • RT1280A, A1280A Output Module Worst-Case Military Conditions, V Parameter Description 1 TTL Output Module Timing t Data-to-Pad HIGH DLH t Data-to-Pad LOW DHL t Enable-to-Pad Z to HIGH ENZH t Enable-to-Pad Z to LOW ENZL t Enable-to-Pad ...

Page 26

RadTolerant FPGAs RT1425A, A1425A Timing Characteristics Table 1-15 • RT1425A, A1425A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock Asynchronous Clear to ...

Page 27

Table 1-16 • RT1425A, A1425A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input F-F Data Hold (w.r.t. IOCLK Pad) INH t Input F-F Data Setup (w.r.t. IOCLK Pad) INSU t Input Data ...

Page 28

RadTolerant FPGAs Table 1-17 • RT1425A, A1425A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input Low to High IOCKH (Pad to I/O Module Input) t Minimum Pulse Width High IOPWH t Minimum Pulse ...

Page 29

RT1460A, A1460A Timing Characteristics Table 1-18 • RT1460A, A1460A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock Asynchronous Clear to Q CLR ...

Page 30

RadTolerant FPGAs Table 1-19 • RT1460A, A1460A I/O and Output Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input F-F Data Hold (w.r.t. IOCLK Pad) INH t Input F-F Data Setup (w.r.t. IOCLK Pad) INSU t ...

Page 31

Table 1-20 • RT1460A, A1460A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input Low to High (Pad to I/O Module Input) IOCKH t Minimum Pulse Width High IOPWH t Minimum Pulse Width Low ...

Page 32

RadTolerant FPGAs RT14100A, A14100A Timing Characteristics Table 1-21 • RT14100A, A14100A Logic and Input Modules Worst-Case Military Conditions, V Parameter Description Logic Module Propagation Delays t Internal Array Module PD t Sequential Clock-to Asynchronous Clear-to-Q CLR Logic Module ...

Page 33

Table 1-22 • RT14100A, A14100A I/O and Output Modules Worst-Case Military Conditions, V Parameter Description I/O Module Sequential Timing t Input Flip-Flop Data Hold INH t Input Flip-Flop Data Setup INSU t Input Data Enable Hold IDEH t Input Data ...

Page 34

RadTolerant FPGAs Table 1-23 • RT14100A, A14100A Clock Networks Worst-Case Military Conditions, V Parameter Description Dedicated (Hard-Wired) I/O Clock Network t Input LOW to HIGH IOCKH (Pad to I/O Module Input) t Minimum Pulse Width HIGH IOPWH t Minimum Pulse ...

Page 35

... Pin Descriptions CLK Clock (Input) RT1020 and A1020B only. TTL clock input for global clock distribution networks. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKA Clock A (Input) Not applicable for RT1020 and A1020B. TTL clock input for global clock distribution networks ...

Page 36

...

Page 37

Package Pin Assignments 84-Pin CQFP Pin #1 Index Figure 2-1 • 84-Pin CQFP (Top View ...

Page 38

... I/O I/O 55 MODE MODE I/O I/O 59 I/O I/O 60 I/O I/O 61 SDI, I/O SDI, Input 62 DCLK, I/O DCLK, Input 63 PRA, I/O PRA, I/O 64 PRB, I/O PRB, I/O 65 I/O I/O 66 I/O I/O 67 I/O I/O 68 I/O I/O 69 I/O I/O 70 I/O I/O v3.1 84-Pin CQFP Pin A1020B RT1020 Number Function Function 71 GND GND 72 I/O I/O 73 I/O I/O 74 I/O I/O 75 I/O I/O 76 I/O I I/O I/O 79 I/O I/O 80 I/O I/O 81 I/O I/O 82 I/O I/O 83 I/O I/O 84 I/O I/O ...

Page 39

CQFP 132131130129128127126125124 Pin #1 Index Figure 2-2 • 132-Pin CQFP (Top View) 107106105104103 ...

Page 40

RadTolerant FPGAs 132-Pin CQFP Pin A1425A RT1425A Number Function Function GND GND 3 SDI, I/O SDI, I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 MODE MODE 10 ...

Page 41

CQFP Pin A1425A RT1425A Number Function Function 106 GND GND 107 108 I/O I/O 109 I/O I/O 110 I/O I/O 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O ...

Page 42

RadTolerant FPGAs 172-Pin CQFP 172 171 170 169 168 167 166 165 164 Pin #1 Index ...

Page 43

CQFP Pin A1280A RT1280A Number Function Function 1 MODE MODE 2 I/O I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 GND GND 8 I/O I/O 9 I/O I/O 10 I/O I/O 11 I/O ...

Page 44

RadTolerant FPGAs 172-Pin CQFP Pin A1280A RT1280A Number Function Function 106 GND GND 107 108 GND GND 109 110 111 I/O I/O 112 I/O I/O 113 V V ...

Page 45

CQFP 196 195 194 193 192 191 190 189 188 Pin #1 Index Figure 2-4 • 196-Pin CQFP (Top View) 155 154 ...

Page 46

RadTolerant FPGAs 196-Pin CQFP Pin A1460A RT1460A Number Function Function 1 GND GND 2 SDI, I/O SDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 ...

Page 47

CQFP Pin A1460A RT1460A Number Function Function 106 I/O I/O 107 I/O I/O 108 I/O I/O 109 I/O I/O 110 111 112 GND GND 113 I/O I/O 114 I/O I/O 115 ...

Page 48

RadTolerant FPGAs 256-Pin CQFP 256 255 254 253 252 251 250 249 248 Pin #1 Index Figure 2-5 • 256-Pin CQFP (Top View) ...

Page 49

CQFP Pin A14100A RT14100A Number Function Function 1 GND GND 2 SDI, I/O SDI, I/O 3 I/O I/O 4 I/O I/O 5 I/O I/O 6 I/O I/O 7 I/O I/O 8 I/O I/O 9 I/O I/O 10 I/O I/O ...

Page 50

RadTolerant FPGAs 256-Pin CQFP Pin A14100A RT14100A Number Function Function 106 I/O I/O 107 I/O I/O 108 I/O I/O 109 I/O I/O 110 GND GND 111 I/O I/O 112 I/O I/O 113 I/O I/O 114 I/O I/O 115 I/O I/O ...

Page 51

CQFP Pin A14100A RT14100A Number Function Function 211 I/O I/O 212 I/O I/O 213 I/O I/O 214 I/O I/O 215 I/O I/O 216 I/O I/O 217 I/O I/O 218 I/O I/O 219 CLKA, I/O CLKA, I/O 220 CLKB, I/O ...

Page 52

...

Page 53

Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( The following pins changed in the v3.0 • Pin ...

Page 54

... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 USA United Kingdom Phone 650.318.4200 Phone +44 (0)1276 401 450 Fax 650 ...

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