A10V20B-PL84C Actel, A10V20B-PL84C Datasheet

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A10V20B-PL84C

Manufacturer Part Number
A10V20B-PL84C
Description
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer
Actel
Datasheet

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Part Number:
A10V20B-PL84C
Manufacturer:
Microsemi SoC
Quantity:
10 000
ACT
F e a t u re s
• 5V and 3.3V Families fully compatible with JEDEC
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
D e s c r ip t i on
The ACT™ 1 Series of field programmable gate arrays
(FPGAs) offers a variety of package, speed, and application
combinations. Devices are implemented in silicon gate,
1-micron two-level metal CMOS, and they employ Actel’s
PLICE
gate array flexibility, high performance, and instant
turnaround through user programming. Device utilization is
typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique
on-chip diagnostic probe capabilities, allowing convenient
testing and debugging. Additional features include an on-chip
clock driver with a hardwired distribution network. The
network provides efficient clock distribution with minimum
skew.
The user-definable I/Os are capable of driving at both TTL
and CMOS drive levels. Available packages include plastic
and ceramic J-leaded chip carriers, ceramic and plastic quad
flatpacks, and ceramic pin grid array.
Apr i l 199 6
© 1996 Actel Corporation
specifications
Place and Route
Analysis to 25 MHz
®
antifuse technology. The unique architecture offers
1 Series FPGAs
®
Packages
A security fuse may be programmed to disable all further
programming and to protect the design from being copied or
reverse engineered.
Pr o d u c t F a m i ly P r o fi l e
Th e D e s i g n e r a n d D e s ig n e r
A d v a n t a g e ™ Sy s t e ms
The ACT 1 device family is supported by Actel’s Designer and
Designer Advantage Systems, allowing logic design
implementation with minimum effort. The systems offer
Microsoft
interfaces and integrate with the resident CAE system to
provide a complete gate array design environment: schematic
capture, simulation, fully automatic place and route, timing
verification, and device programming. The systems also
include the ACTmap
and the ACTgen
generator for counters, adders, and other structural blocks.
Device
Capacity
Logic Modules
Flip-Flops (maximum)
Routing Resources
User I/Os (maximum)
Packages:
Performance
Note:
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Horizontal Tracks/Channel
Vertical Tracks/Column
PLICE Antifuse Elements
5 V Data Rate (maximum)
3.3 V Data Rate (maximum)
See Product Plan on page 1-286 for package availability.
®
Windows
Macro Builder, a powerful macro function
VHDL optimization and synthesis tool
and X Windows
100 PQFP
A10V10B
84 CPGA
44 PLCC
68 PLCC
80 VQFP
A1010B
112,000
75 MHz
55 MHz
1,200
3,000
295
147
30
12
22
13
57
graphical user
100 PQFP
A10V20B
84 CPGA
84 CQFP
44 PLCC
68 PLCC
84 PLCC
80 VQFP
A1020B
186,000
75 MHz
55 MHz
2,000
6,000
1-283
547
273
50
20
22
13
69

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A10V20B-PL84C Summary of contents

Page 1

... The systems also ™ include the ACTmap VHDL optimization and synthesis tool ™ and the ACTgen Macro Builder, a powerful macro function generator for counters, adders, and other structural blocks. A1020B A10V20B 1,200 2,000 3,000 6,000 ...

Page 2

The systems are available for 386/486/Pentium ™ ™ HP and Sun workstations and for running Viewlogic Figure 1 • Partial View of an ACT 1 Device ACT Struct partial view of an ...

Page 3

... These pins allow the user to observe any two internal signals by entering the appropriate net name in the diagnostic software. Signals may be viewed on a logic analyzer using ® Actel’s Actionprobe diagnostic tools. The probe pins can also be used as user-defined I/Os when debugging is finished. Orderin g Infor ...

Page 4

... Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) Applications Commercial Availability Industrial M = Military B = MIL-STD-883 De vice R es ources Device Logic Modules A1010B, A10V10B 295 A1020B, A10V20B 547 1-286 Speed Grade* Std –1 –2 –3 — — — — — ...

Page 5

Pin ption CLK Clock (Input) TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) ...

Page 6

Ele c trical Spe ci fica t i ons (5V ) Symbol Parameter –10 mA –6 mA – ...

Page 7

... I/O. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. ...

Page 8

... Device Type A1010B A1010B A1020B A1020B 3.2 3.7 A10V10B 10.9 22.1 A10V20B 11.6 31.2 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the 4.1 4.6 circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation ...

Page 9

Fu nctional est s AC timing for logic module internal delays is determined after place and route. The DirectTime Analyzer utility displays actual timing parameters for circuit delays. ACT 1 devices are AC tested to ...

Page 10

... This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 1 family’s antifuses, fabricated in 1.0 micron lithography, offer nominal levels of 200 ohms resistance and 7 ...

Page 11

Timing Derating A best case timing derating factor of 0.45 is used to reflect best case processing. Note that this factor is relative to the Timing Derati ng Fact and ...

Page 12

Te mp erature and age tors (n ormali zed Commercial 2.7 ...

Page 13

Parameter Meas Output Buffer Delays GND 50% 50 1.5 V PAD 1 DLH DHL AC Test Loads Load 1 (Used to measure propagation delay) To the ...

Page 14

Se q uen tial Timi ng C har act Flip-Flops and Latches SUD CLK E Q PRE, CLR Note: D represents all data functions involving for multiplexed flip-flops. ...

Page 15

Timi (Worst-Case Commercial Conditions, V Logic Module Propagation Delays Parameter Description t Single Module PD1 t Dual Module Macros PD2 t Sequential Clk ...

Page 16

ACT 1 Timing Char act (Worst-Case Commercial Conditions) Input Module Propagation Delays Parameter Description t Pad to Y High INYH t Pad to Y Low INYL Input Module Predicted Routing Delays t FO=1 Routing Delay ...

Page 17

... THL Notes: 1. Delays based loading. 2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125. (continued) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 6 ...

Page 18

... CLK, I/O MODE 52 54 VCC SDI, I/O 55 DCLK, I PRA, I/O PRB, I GND 68-Pin PLCC A1010B, A10V10B A1020B, A10V20B Function Functions VCC VCC GND GND GND GND VCC VCC VCC VCC GND GND VCC VCC GND GND CLK, I/O CLK, I/O MODE MODE ...

Page 19

... NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. (continued A1020B 84-Pin PLCC A1020B, A10V20B Function VCC NC GND GND VCC VCC VCC GND VCC GND ...

Page 20

Pa c kag e Pin Assi gnm 100-Pin PQFP 100 1 A1010B Pin Function PRB, I/O 13 GND 19 VCC ...

Page 21

... I/O 52 GND 53 VCC 54 I/O 55 I/O 56 I/O 57 VCC 58 GND 59 VCC 60 I/O 61 I/O 68 I/O 74 ™ eri es FPG As A1010B, A10V10B A1020B, A10V20B Function Function GND GND CLK, I/O CLK, I/O MODE MODE VCC VCC NC I/O NC I/O NC I/O SDI, I/O SDI, I/O DCLK, I/O DCLK, I/O PRA, I/O PRA, I PRB, I/O PRB, I/O GND GND ...

Page 22

Pa c kag e Pin Assi gnm 84-Pin CPGA Pin A1010B Function A11 PRA, I VCC B7 GND B10 PRB, I/O ...

Page 23

Pack age Pin ent s 84-Pin CQFP 84 Pin #1 Index 1 Pin A1020B Function GND 8 GND 14 VCC 15 VCC 22 VCC 29 GND 35 VCC 49 GND 50 GND ...

Page 24

1-306 ...

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