A10V20B-PL84C Actel, A10V20B-PL84C Datasheet
A10V20B-PL84C
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A10V20B-PL84C Summary of contents
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... The systems also ™ include the ACTmap VHDL optimization and synthesis tool ™ and the ACTgen Macro Builder, a powerful macro function generator for counters, adders, and other structural blocks. A1020B A10V20B 1,200 2,000 3,000 6,000 ...
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The systems are available for 386/486/Pentium ™ ™ HP and Sun workstations and for running Viewlogic Figure 1 • Partial View of an ACT 1 Device ACT Struct partial view of an ...
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... These pins allow the user to observe any two internal signals by entering the appropriate net name in the diagnostic software. Signals may be viewed on a logic analyzer using ® Actel’s Actionprobe diagnostic tools. The probe pins can also be used as user-defined I/Os when debugging is finished. Orderin g Infor ...
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... Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) Applications Commercial Availability Industrial M = Military B = MIL-STD-883 De vice R es ources Device Logic Modules A1010B, A10V10B 295 A1020B, A10V20B 547 1-286 Speed Grade* Std –1 –2 –3 — — — — — ...
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Pin ption CLK Clock (Input) TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) ...
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Ele c trical Spe ci fica t i ons (5V ) Symbol Parameter –10 mA –6 mA – ...
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... I/O. The power can be divided into two components: static and active. Static Power Component Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. ...
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... Device Type A1010B A1010B A1020B A1020B 3.2 3.7 A10V10B 10.9 22.1 A10V20B 11.6 31.2 Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the 4.1 4.6 circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation ...
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Fu nctional est s AC timing for logic module internal delays is determined after place and route. The DirectTime Analyzer utility displays actual timing parameters for circuit delays. ACT 1 devices are AC tested to ...
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... This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 1 family’s antifuses, fabricated in 1.0 micron lithography, offer nominal levels of 200 ohms resistance and 7 ...
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Timing Derating A best case timing derating factor of 0.45 is used to reflect best case processing. Note that this factor is relative to the Timing Derati ng Fact and ...
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Te mp erature and age tors (n ormali zed Commercial 2.7 ...
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Parameter Meas Output Buffer Delays GND 50% 50 1.5 V PAD 1 DLH DHL AC Test Loads Load 1 (Used to measure propagation delay) To the ...
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Se q uen tial Timi ng C har act Flip-Flops and Latches SUD CLK E Q PRE, CLR Note: D represents all data functions involving for multiplexed flip-flops. ...
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Timi (Worst-Case Commercial Conditions, V Logic Module Propagation Delays Parameter Description t Single Module PD1 t Dual Module Macros PD2 t Sequential Clk ...
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ACT 1 Timing Char act (Worst-Case Commercial Conditions) Input Module Propagation Delays Parameter Description t Pad to Y High INYH t Pad to Y Low INYL Input Module Predicted Routing Delays t FO=1 Routing Delay ...
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... THL Notes: 1. Delays based loading. 2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125. (continued) ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 6 ...
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... CLK, I/O MODE 52 54 VCC SDI, I/O 55 DCLK, I PRA, I/O PRB, I GND 68-Pin PLCC A1010B, A10V10B A1020B, A10V20B Function Functions VCC VCC GND GND GND GND VCC VCC VCC VCC GND GND VCC VCC GND GND CLK, I/O CLK, I/O MODE MODE ...
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... NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. (continued A1020B 84-Pin PLCC A1020B, A10V20B Function VCC NC GND GND VCC VCC VCC GND VCC GND ...
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Pa c kag e Pin Assi gnm 100-Pin PQFP 100 1 A1010B Pin Function PRB, I/O 13 GND 19 VCC ...
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... I/O 52 GND 53 VCC 54 I/O 55 I/O 56 I/O 57 VCC 58 GND 59 VCC 60 I/O 61 I/O 68 I/O 74 ™ eri es FPG As A1010B, A10V10B A1020B, A10V20B Function Function GND GND CLK, I/O CLK, I/O MODE MODE VCC VCC NC I/O NC I/O NC I/O SDI, I/O SDI, I/O DCLK, I/O DCLK, I/O PRA, I/O PRA, I PRB, I/O PRB, I/O GND GND ...
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Pa c kag e Pin Assi gnm 84-Pin CPGA Pin A1010B Function A11 PRA, I VCC B7 GND B10 PRB, I/O ...
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Pack age Pin ent s 84-Pin CQFP 84 Pin #1 Index 1 Pin A1020B Function GND 8 GND 14 VCC 15 VCC 22 VCC 29 GND 35 VCC 49 GND 50 GND ...
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1-306 ...