A1240A-PL84I Actel, A1240A-PL84I Datasheet
A1240A-PL84I
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A1240A-PL84I Summary of contents
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... Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz • Two High-Speed, Low-Skew Clock Networks • I/O Drive • Nonvolatile, User Programmable • Logic Fully Tested Prior to Shipment • 1.0-micron CMOS Technology A1225A A1240A 2,500 4,000 6,250 10,000 63 100 25 ...
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... The ACT™ 2 family represents Actel’s second generation of field programmable gate arrays (FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s ...
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... Ceramic Pin Grid Array (PG) 100-pin Plastic Quad Flat Pack (PQ) 100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ) 84-pin Plastic Leaded Chip Carrier (PL) A1240A Device 132-pin Ceramic Pin Grid Array (PG) 176-pin Thin (1.4 mm) Quad Flat Pack (TQ) 144-pin Plastic Quad Flat Pack (PQ) 84-pin Plastic Leaded Chip Carrier (PL) ...
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Abs axim ngs Free air temperature range Symbol Parameter V DC Supply Voltage –0.5 to +7.0 ...
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... I/O. The power can be divided into two components: static and active. S tat ponen t Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even Maximum junction temperature is 150° ...
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... Average second routed array clock rate in MHz q2 Fi xed Ca paci ta nce Val ues fo r Act (pF ) Device Type A1225A A1240A A1280A D et erm i nin chi quenc y 5.8 To determine the switching frequency for a design, you must 12.9 have a detailed understanding of the data input values to the circuit ...
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... INYL IRD2 2.0 ns INH t = 4.0 ns INSU t = 4.7 ns INGL ARRAY CLOCKS 256 CKH F = 100 MHz MAX *Values shown for A1240A-2 at worst-case commercial conditions. Internal Delays Predicted Routing Delays Combinatorial Logic Module = 4.8 ns † 1.4 ns RD1 RD2 t = 3.1 ns RD4 t = 4.7 ns ...
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put Buf lay GND 50% 50 1.5 V PAD 1 ...
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Inpu t Buffe r Lat che s DATA PAD CLK DATA G CLK Out put B uffer ...
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(Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Single Module PD1 t Sequential Clk to Q ...
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... ENLZ Pad High GLH Pad Low GHL d Delta Low to High TLH d Delta High to Low THL Note: 1. Delays based loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. 14 (continued) ‘–2’ Speed ‘–1’ Speed Min. Max. Min. Max. 8.0 9.0 10.1 11.4 8.9 10.0 11.6 13.2 7 ...
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(Worst-Case Commercial Conditions Logic ...
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cia l Cond it ion s) Input Module Propagation ...
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... ENLZ Pad High GLH Pad Low GHL d Delta Low to High TLH d Delta High to Low THL Note: 1. Delays based loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. (continued) ‘–2’ Speed ‘–1’ Speed Min. Max. Min. Max. 8.0 9.0 10.1 11.4 8.9 10.0 11.7 13.2 7.1 8 ...
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(Worst-Case Commercial Conditions Logic Module Propagation Delays Parameter Description t Single Module PD1 t Sequential Clk to Q ...
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...
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... ENLZ Pad High GLH Pad Low GHL d Delta Low to High TLH d Delta High to Low THL Note: 1. Delays based loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. 20 (continued) ‘–2’ Speed ‘–1’ Speed Min. Max. Min. Max. 8.1 9.0 10.2 11.4 9.0 10.0 11.8 13.2 7 ...
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CLKA Clock A (Input) TTL Clock input for clock distribution networks. The Clock input is buffered ...
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... Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND 84-Pin PLCC A1240A Function A1280A Function CLKB, I/O CLKB, I/O PRB, I/O PRB, I/O GND GND DCLK, I/O DCLK, I/O MODE ...
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... VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND 84-Pin PLCC A1240A Function A1280A Function VCC VCC GND GND GND GND VCC VCC VCC VCC ...
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100 100 1 Pin Number A1225A Function 2 DCLK, I/O 4 MODE 9 GND 16 VCC 17 VCC 22 ...
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144 (cont i nued) 144-Pin ...
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... GND 81 GND 88 GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND Pin Number A1240A Function 89 VCC 90 VCC 91 VCC 92 VCC 93 VCC 100 GND 101 GND ...
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160 160 1 (cont i ...
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Pin Number A1280A Function 2 DCLK, I/O 6 VCC 11 GND 16 PRB, I/O 18 CLKB, I/O 20 VCC 21 CLKA, I/O 23 PRA, I/O 30 GND 35 VCC 38 SDI, I/O 40 GND ...
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100 VQF P 100 1 100 ...
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176 176 1 30 (cont i nued) 176-Pin TQFP v4.0 ™ ...
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... NC 147 I/O 151 I/O 152 I/O 154 GND 155 VCC 156 I/O 158 NC 160 I/O 161 I/O 165 VCC 166 I/O 168 GND 170 I/O 173 I/O 175 v4.0 A1240A Function A1280A Function I/O GND GND NC I/O NC I/O GND GND VCC VCC GND GND VCC VCC VCC VCC NC I/O NC I/O NC VCC I/O ...
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172 CQF P Pin #1 Index 1 172-Pin CQFP Pin Number A1280A Function 1 MODE 7 GND 12 VCC 17 GND 22 ...
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100 Pin Number A1225A Function A4 ...
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... Orientation Pin Pin Number v4.0 ™ A1240A Function G2 VCC G3 VCC G4 VCC G10 VCC G11 VCC G12 VCC G13 VCC H13 GND J2 GND J3 GND J11 GND K7 ...
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176 ...
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The following table lists critical changes that were made in the current version of the document. Previous version Changes in current version (production (unmarked) v4.0.1–web-only) In the 176-Pin CPGA package, ...
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v4.0 37 ...
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... Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44 (0)1256 305600 Fax: +44 (0)1256 355420 http://www.actel.com Actel Corporation ...