HY628100ALT1-55 HEI, HY628100ALT1-55 Datasheet
HY628100ALT1-55
Related parts for HY628100ALT1-55
HY628100ALT1-55 Summary of contents
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DESCRIPTION The HY628100A is a high speed, low power and 1M bit CMOS Static Random Access Memory organized as 131,072 words by 8bit. The HY628100A uses high performance process technology and designed for high speed low power circuit technology. It ...
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... ORDERING INFORMATION Part No. Speed HY628100AG 55/70/85 HY628100ALG 55/70/85 HY628100ALLG 55/70/85 HY628100AT1 55/70/85 HY628100ALT1 55/70/85 HY628100ALLT1 55/70/85 Comment : 50ns is available with 30pF test load. ABSOLUTE MAXIMUM RATING (1) Symbol Vcc Power Supply, Input/Output Voltage IN, OUT T Operating Temperature A T Storage Temperature STG P Power Dissipation D I Data Output Current OUT T Lead Soldering Temperature & ...
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DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V 10 unless otherwise specified A Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Icc Operating Power Supply Current I Average Operating CC1 Current ...
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AC TEST CONDITIONS (Normal), unless otherwise specified A PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Comment * : Test load is 30pF for ...
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TIMING DIAGRAM READ CYCLE 1 ADDR OE CS1 CS2 High-Z Data Out Note(READ CYCLE): 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels ...
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WRITE CYCLE 1(/WE Controlled) ADDR CS1 CS2 WE Data In Data Data Undefined Out WRITE CYCLE 2 (/CS1 Controlled) ADDR tAS CS1 CS2 WE Data In High-Z Data High-Z Out Rev.05 /Feb.99 tWC tAW tCW tWP tAS tDW tOHZ tWC ...
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WRITE CYCLE 3 (CS2 Controlled) ADDR tAS CS1 CS2 WE Data In High-Z High-Z Data Out Notes(WRITE CYCLE write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition ...
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DATA RETENTION ELECTRIC CHARACTERISTIC SYM Parameter V Vcc for Data Retention DR I Data Retention Current CCDR tCDR Chip Deselect to Data Retention Time tR Operating Recovery Time Notes: 1. Typical values are under the condition tRC ...
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RELIABILITY SPEC . TEST MODE TEST SPEC. ESD HBM > 2000V MM > 250V LATCH - UP < -100mA > 100mA PACKAGE INFORMATION 32pin 525mil Small Outline Package(G) 0.810(20.574) 0.804(20.422) 0.020(0.508) 0.050(1.27)BSC 0.014(0.356) 32pin 8x20mm Thin Small Outline Package Standard(T1) ...