MK2049-34SI ICST, MK2049-34SI Datasheet
MK2049-34SI
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MK2049-34SI Summary of contents
Page 1
... This allows for the generation of clocks frequency-locked and phase-locked kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-34 can also accept input clock and provide the same output for loop timing. All outputs are frequency locked together and to the input. ...
Page 2
... Connect the loop filter ceramic capacitors and resistor between this pin and CAP1. Connect a 10-200k resistor to ground. Contact ICS applications dept. at 408-297-1201 for the recommended value for your app. Frequency Select 0. Determines CLK input/outputs per tables on page 4. 2 MK2049-34 Revision 121400 ...
Page 3
... Absolute Maximums may affect device reliability. MDS 2049-34 C Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com 3.3 V Communications Clock PLL Conditions Minimum Referenced to GND -0.5 MK2049-34SI -40 Max of 10 seconds -65 3.15 2 IOH=-4 mA VDD-0.4 IOH=- ...
Page 4
... MK2049-34 Output Decoding Table – Loop Timing Mode (MHz) ICLK FS3 FS2 FS1 FS0 1.544 2.048 MK2049-34 Output Decoding Table – Buffer Mode (MHz) ICLK FS3 FS2 FS1 FS0 ...
Page 5
... MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs. INPUT AND OUTPUT SYNCHRONIZATION As shown in the tables on page 4, the MK2049-34 offers a Zero Delay feature in all selections. There is an internal feedback path between ICLK and the output clocks, providing a fixed phase relationship between the input and output, a requirement in many communications systems ...
Page 6
... In fact, the input and output clocks probably are locked, and the MK2049 will have zero delay to the average position of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources are NOT SUITABLE for this since they have high jitter at low frequencies ...
Page 7
... The typical telecom reference frequency is accurate to much less than 1 ppm, so the MK2049 may lock and run properly even if the board capacitance is not adjusted with these fixed capacitors. However, ICS MicroClock recommends that the adjustment capacitors be included to minimize the effects of variation in individual crystals, temperature, and aging ...
Page 8
... The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal. External stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should use short traces between the MK2049 and the crystal ...
Page 9
... Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com 3.3 V Communications Clock PLL Minimum Typical Maximum - -20 20 Note 1 7 none none 250 35 9 MK2049-34 Units °C ppm ppm ppm ppm pF pF none Ohms Revision 121400 ...
Page 10
... determine the value of the crystal capacitors: 1. Connect VDD of the MK2049 to 3.3 V. Connect pin 18 of the MK2049 to the second power supply. Adjust the voltage on pin 18 to 0.0 V. Measure and record the frequency of the CLK or CLK/2 output . 2. Adjust the voltage on pin 18 to 3.3 V. Measure and record the frequency of the same output. ...
Page 11
... ICS product for use in life support devices or critical medical instruments. MDS 2049-34 C Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com 3.3 V Communications Clock PLL 45° Marking MK2049-34SI MK2049-34SI 11 MK2049-34 20 pin SOIC Inches Inches Millimeters Millimeters Symbol Min Max ...