WM8141CFT/V Wolfson Microelectronics plc, WM8141CFT/V Datasheet
WM8141CFT/V
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WM8141CFT/V Summary of contents
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CIS/CCD Analogue Front End/Digitiser DESCRIPTION The WM8141 is a 12-bit analogue front end/digitiser that processes and digitises the analogue output signals from CCDs or Contact Image Sensors (CIS). The device can be operated as either a three channel ...
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... VRLC/ Analogue IO VBIAS 19 BINP Analogue input 20 GINP Analogue input 21 RINP Analogue input 22 OEB Digital input WOLFSON MICROELECTRONICS LTD ORDERING INFORMATION DEVICE WM8141CFT/V 24 SDI/DNA SEN/STB 23 OEB 22 21 RINP GINP 20 BINP 19 VRLC/VBIAS 18 17 VRX DESCRIPTION Hi-Z digital 12-bit bi-directional bus. There are several modes: Hi-Z: when OEB = 1 ...
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Production Data PIN NAME TYPE 23 SEN/STB Digital input 24 SDI/DNA Digital input 25 SCK/RNW Digital input 26 RLC/ Digital input ACYC 27 VSMP Digital input 28 MCLK Digital input 29 DGND Supply 30 OP[0] Digital output 31 OP[1] Digital ...
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WM8141 RECOMMENDED OPERATING CONDITIONS CONDITION Operating temperature range Digital supply voltages (5V operation) Digital supply voltages (3.3V operation) Analogue supply voltage (5V operation) Analogue supply voltage (3.3V operation) POSSIBLE POWER SUPPLY COMBINATIONS COMBINATION ELECTRICAL CHARACTERISTICS ANALOGUE CHARACTERISTICS ...
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Production Data Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T PARAMETER VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current RLCDAC resolution RLCDAC step ...
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WM8141 ANALOGUE CHARACTERISTICS (3.3V OPERATION) Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, T PARAMETER Overall System Specification Including CDS, PGA, OFFSET and ADC Functions. Full-scale input voltage range (see Note 1) ...
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Production Data Test Conditions AVDD = DVDD1 = DVDD2 = 2.97V to 3.63V, AGND = DGND = 0V, T PARAMETER Supply Currents Total supply current – active Total analogue supply current – active Digital logic supply current, DVDD1 – active ...
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WM8141 INPUT VIDEO SAMPLING MCLK t VSMP INPUT VIDEO Figure 1 Input Video Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T PARAMETER MCLK period MCLK high period MCLK low period ...
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Production Data OEB OP[11:0] Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T PARAMETER Output propagation delay Output enable time Output disable time SERIAL INTERFACE ...
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WM8141 PARALLEL INTERFACE t STB STB t ASU Hi-Z OP[11:4] ADDRESS IN ADC DATA OUT t ADLS DNA t OPZ RNW Figure 5 Parallel Interface Diagram Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND ...
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Production Data DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8141 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal ...
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WM8141 Figure 6 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 6 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period. The ...
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Production Data R /CL (CDSREF = 00 /CL (CDSREF = 01 /CL (CDSREF = 10 /CL (CDSREF = 11) S Figure 8 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing ...
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WM8141 The INPUT SAMPLING BLOCK produces an effective input voltage V difference between the input video level V difference between the input video level V optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of ...
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Production Data OUTPUT FORMATS The digital data output from the ADC is available to the user in either 12-bit parallel or 8/6/4-bit wide multiplexed formats by setting control bits MUXOP[1:0]. Latency of valid output data with respect to VSMP is ...
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WM8141 CONTROL INTERFACE The internal control registers are programmable via the serial or parallel digital control interface. The register contents can also be read back via the parallel interface on OP[11:4], or via the serial interface on pin OP[11]/SDO. SERIAL ...
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Production Data OP[11:4] RNW Figure 14 Parallel Interface Register Write PARALLEL INTERFACE: REGISTER READ-BACK Figure 15 shows register read-back in parallel mode. Read-back is initiated by writing the 6-bit address (a5, 1, a3, a2, a1, a0) into OP[9:4] by pulsing ...
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WM8141 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP (VDEL = 000) INTVSMP (VDEL = 001) ...
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Production Data LINE-BY-LINE OPERATION Certain linear sensors (e.g Contact Image Sensors) give colour output on a line-by-line basis. i.e a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In ...
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WM8141 OPERATING MODES Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE 1 Colour Yes Pixel-by-Pixel 2 Monochrome/ Yes Colour Line-by-Line 3 Fast ...
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Production Data OPERATING MODE TIMING DIAGRAMS The following diagrams show 12-bit parallel format output and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both ...
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WM8141 OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11) Figure 21 Mode 4 Operation OP[11:0] (DEL = 00) OP[11:0] (DEL = 01) OP[11:0] (DEL = 10) OP[11:0] (DEL = 11) Figure 22 ...
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Production Data DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8141. The register map is programmed by writing (in serial or parallel) the required codes to the ...
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WM8141 REGISTER BIT BIT NO NAME(S) Setup 1:0 MUXOP[1:0] Register 2 2 INVOP 3 VRLCEXT 5 RLCDACRNG 7:6 DEL[1:0] Setup 3:0 RLCV[3:0] Register 3 5:4 CDSREF[1:0] 7:6 CHAN[1:0] Software Reset Auto-cycle Reset Setup 0 LINEBYLINE Register 4 1 ACYCNRLC 2 ...
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Production Data REGISTER BIT BIT NO NAME(S) Setup 0 VSMPDET Register 5 3:1 VDEL[2:0] 4 POSNNEG Setup 3:0 SELDIS[3:0] Register 6 Table 7 Register Control Bits WOLFSON MICROELECTRONICS LTD DEFAULT DESCRIPTION Normal operation, signal on VSMP input ...
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WM8141 APPLICATIONS RECOMMENDATIONS INTRODUCTION The WM8141 is a mixed signal device, therefore careful PCB layout is required. The following section contains PCB layout guidelines, which are recommended for optimal performance from the WM8141, and some typical applications circuits. PCB LAYOUT ...
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Production Data MONOCHROME CCD Figure 24 Block Diagram of Monochrome CCD Application, AC Coupled NAME Set-up register 1 Set-up register 2 Set-up register 3 Set-up register 4 Set-up register 5 Set-up register 6 Table 8 WOLFSON MICROELECTRONICS LTD C S ...
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WM8141 COLOUR PIXEL-BY-PIXEL Figure 25 Block Diagram of Colour Pixel-By-Pixel Application, AC Coupled NAME Set-up register 1 Set-up register 2 Set-up register 3 Set-up register 4 Set-up register 5 Set-up register 6 Table 9 WOLFSON MICROELECTRONICS LTD ...
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Production Data COLOUR LINE-BY-LINE Maximum pixel rate = 1.5Mpixels/second (Mode 6) Maximum pixel rate = 2Mpixels/second (Mode 2) Maximum pixel rate = 4Mpixels/second (Mode 3) Maximum pixel rate = 6Mpixels/second (Mode 4) Figure 26 Block Diagram Of Colour Line-By-Line Application, ...
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WM8141 RECOMMENDED EXTERNAL COMPONENTS DVDD C1 C2 DGND Video Inputs Timing Signals Interface Controls NOTES: 1. C1-9 should be fitted as close to WM8141 as possible. 2. AGND and DGND should be connected as close to WM8141 as possible. Figure ...
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Production Data PACKAGE DIMENSIONS FT: 32 PIN TQFP ( 1.4 mm Dimensions Symbols (mm) MIN NOM A ----- ----- A 0.05 ----- 1 A 1.35 1.40 2 ...