AK4565VF AKM Asahi Kasei Microsystems, AK4565VF Datasheet

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AK4565VF

Manufacturer Part Number
AK4565VF
Description
AK4565VFLOW POWER 20BIT CODEC WITH BUILT IN ALC
Manufacturer
AKM Asahi Kasei Microsystems
Datasheet

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ASAHI KASEI
MS0132-E-01
The AK4565 is a low power voltage, 20bit CODEC. The recording feature includes four stereo inputs
selector which switches among microphone and line inputs etc. And the input PGA has an ALC function,
making it suitable for microphone application. The AK4565 has a dedicated power supply pin for digital
I/F, which can support I/O level down to 1.5V. The AK4565 can be powered-down partly and is suitable
for portable application.
10. Power Supply
11. Power Supply Current
12. Ta = - 40
13. Package: 28pin VSOP
14. AK4563A pin-compatible
1. Resolution: 20bits
2. Recording Functions
3. Playback Function
4. Power Management
5. CODEC
6. Master Clock: 256fs/384fs
7. Sampling Rate: 8kHz
8. Audio Data Interface Format: MSB-First, 2’s compliment
9. P Interface: 4-wire
Four Stereo Inputs Selector
Input PGA (Programmable Gain Amplifier) with ALC (Automatic Level Control)
FADEIN / FADEOUT
Digital HPF for DC-offset cancellation (fc=3.7Hz@fs=48kHz)
Digital De-emphasis Filter (tc = 50/15 s, fs=32k, 44.1k and 48kHz)
Single-ended Inputs/Outputs
Input / Output Level: 1.5Vpp@VREF=2.5V (= 0.6 x VREF)
S/(N+D): 83dB(ADC), 86dB(DAC) @VREF=2.5V
DR, S/N: 87dB(ADC), 91dB(DAC) @VREF=2.5V
ADC: 20bit MSB justified, I
DAC: 20bit MSB justified, 16/20bit LSB justified, I
CODEC, IPGA: 2.3
Digital I/F: 1.5
ALL Power ON: 12.5mA
IPGA + ADC: 8mA
DAC: 5.5mA
85 º C
3.6V(typ.2.5V)
50kHz
Low Power 20bit CODEC with built-in ALC
3.6V (typ.2.5V)
GENERAL DESCRIPTION
2
S
FEATURES
- 1 -
2
S
AK4565
[AK4565]
2003/05

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AK4565VF Summary of contents

Page 1

ASAHI KASEI Low Power 20bit CODEC with built-in ALC The AK4565 is a low power voltage, 20bit CODEC. The recording feature includes four stereo inputs selector which switches among microphone and line inputs etc. And the input PGA has an ...

Page 2

INTL0 INTL1 IPGA EXTL LIN INTR0 INTR1 EXTR RIN LOUT ROUT VCOM VREF VA AGND MS0132-E-01 ADC HPF DAC De-emp Control Register I/F CSN CCLK CDTI CDTO Figure 1. AK4565 Block Diagram - 2 - LRCK BCLK Audio I/F SDTO0 ...

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... ASAHI KASEI n Ordering Guide AK4565VF -40 AKD4565 Evaluation board for AK4565 n Pin Layout LOUT 1 ROUT 2 INTL1 3 INTR1 4 INTL0 5 6 INTR0 EXTL 7 EXTR 8 LIN 9 RIN 10 VCOM 11 AGND VREF 14 MS0132-E-01 +85 C 28pin VSOP (0.65mm pitch AK4565 23 Top 22 View ...

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No. Pin Name I/O 1 LOUT O Lch Analog Output Pin 2 ROUT O Rch Analog Output Pin 3 INTL1 I Lch INT #1 Input Pin 4 INTR1 I Rch INT #1 Input Pin 5 INTL0 I Lch INT #0 ...

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ASAHI KASEI (AGND, DGND=0V; Note 1) Parameter Power Supply Analog (VA pin) Digital 1 (VD pin) Digital 2 (VT pin) | DGND – AGND | (Note 2) Input Current, Any Pin Except Supplies Analog Input Voltage (Note 3) Digital Input ...

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ASAHI KASEI (Ta=25 C; VA, VD, VT=2.5V; fs=48kHz; Signal Frequency =1kHz; Measurement frequency = 10Hz 20kHz; Unless otherwise specified) Parameter Input PGA Characteristics (IPGA): Input Voltage (INTL1-0, INTR1-0, EXTL, EXTR, LIN and RIN pins) (Note 7) Input Resistance: MIC (INTL1-0, ...

Page 7

ASAHI KASEI (Ta=25 C; VA, VD=2.3 3.6V; VT=1.5 3.6V; fs=48kHz; De-emphasis = OFF) Parameter ADC Digital Filter (Decimation LPF): Passband (Note 12) 0.1dB -1.0dB -3.0dB Stopband (Note 12) Passband Ripple Stopband Attenuation Group Delay (Note 13) Group Delay Distortion ADC ...

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ASAHI KASEI (Ta=25 C; VA, VD=2.3 3.6V, VT=1.5 3.6V) Parameter Input High Level Voltage Input Low Level Voltage Output High Level Voltage: Iout=-400 A Output Low Level Voltage: Iout=400 A Input Leakage Current (Ta=25 C; VA, VD=2.3 3.6V, VT=1.5 3.6V; ...

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ASAHI KASEI n Timing Diagram LRCK BCLK SDTO0,1 SDTI Figure 2. Audio Data Input/Output Timing (Audio I/F Format: No.0) CSN tCSS CCLK CDTI CDTO Figure 3. WRITE/READ Command Input Timing CSN CCLK CDTI D4 CDTO MS0132-E-01 tBLR tBLKH tDLR D15 ...

Page 10

ASAHI KASEI CSN CCLK A3 CDTI Hi-Z CDTO CSN CCLK CDTI CDTO D4 PDN SDTO0,1 MS0132-E-01 tCKH2 A4 tDCD D0 D1 Figure 5. READ Data Output Timing 1 tCSH Figure 6. READ Data Input Timing 2 tPDW ...

Page 11

System Clock Input The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs ). The master clock (MCLK) should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can ...

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Power Supply PDN pin PDN pin may be “L” at power-up. ADC Internal PD State AIN SDTO0,1 DAC Internal PD State SDTI AOUT Control register INIT-1 W rite to register Inhibit-1 Read from register Inhibit-1 External clocks Figure 8. Power-up/Power-down ...

Page 13

ASAHI KASEI n Digital High Pass Filter (HPF) The AK4565 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the IPGA and ADC. The cut-off frequency of the HPF is 3.7Hz at fs=48kHz and it is attenuated ...

Page 14

LRCK( BCLK(i:64fs) SDTO0,1( SDTI(i) Don’t Care 19 19:MSB, 0:LSB Lch Data LRCK( BCLK(i:64fs) SDTO0,1( SDTI( 19:MSB, 0:LSB Lch ...

Page 15

ASAHI KASEI n ALC Operation 1. ALC Limiter Operation During the ALC limiter operation, when either Lch or Rch exceed ALC limiter detection level (LMTH), IPGA value is attenuated by ALC limiter ATT step (LMAT1-0) automatically. Then the IPGA value ...

Page 16

ASAHI KASEI The following registers should be changed during the ALC operation. LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELMN WR (Power Management Control & Signal Select registers) WR (ZTM1-0, WTM1-0, LTM1- Finish ALC mode and return to ...

Page 17

ASAHI KASEI n FADEIN Mode In FADEIN Mode, the IPGA value increases gradually by the step set by FDATT bit when FDIN bit changes from “0” to “1”. The FADEIN period is set by FDTM1-0 bits. The FADEIN operation is ...

Page 18

ASAHI KASEI n FADEOUT Mode In FADEOUT mode, the present IPGA value decreases gradually down to the MUTE state when FDOUT bit changes from “0” to “1”. This operation is done by the zero crossing detection. If the large signal ...

Page 19

ASAHI KASEI n Operation of IPGA [Writing operation at ALC Enable] Writing to IPGA6-0 bit is ignored during ALC operation and FADEIN/OUT operation. [Writing operation at ALC Disable] When writing to the control register continually, the control register should be ...

Page 20

ASAHI KASEI n Register Map Addr Register Name 00H Input Select 01H Power Management 02H Mode Control 03H Timer Select FDTM1 04H ALC Mode Control 1 05H ALC Mode Control 2 06H Operation Mode 07H Input PGA Control 08H Test ...

Page 21

Addr Register Name 01H Power Management R/W Default PM0: IPGA and ALC circuit power control. 0: Power OFF 1: Power ON (Default) After exiting PM0 = “0”, IPGA goes default value. PM1: ADC power control. 0: Power OFF 1: Power ...

Page 22

Organization of Power Management Bit 1) All Power ON PM0: 1 PM1: 1 PM2: 1 PM3 REC Mode PM0: 1 PM1: 1 PM2: 0 PM3 REC monitor PM0: 1 PM1: 1 PM2: 0 PM3 ...

Page 23

ASAHI KASEI Addr Register Name 02H Mode Control R/W Default DEM1-0: Select De-emphasis frequency The AK4565 includes the digital de-emphasis filter (tc = 50/ IIR filter. The filter corresponds to three sampling frequencies (32kHz, 44,1kHz and 48kHz). The ...

Page 24

Addr Register Name 03H Timer Select FDTM1 R/W Default LTM1-0: ALC Limiter Period at ZELMN = “1” The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by the period specified by LTM1-0 ...

Page 25

ASAHI KASEI FDTM1-0: FADEIN/OUT Period Setting The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT bits are set “1”. When IPGA of each L/R channel do zero crossing or timeout independently, the IPGA ...

Page 26

ASAHI KASEI Addr Register Name 04H ALC Mode Control 1 R/W Default LMTH: Auto Limiter Detection Level / Auto Recovery Waiting Counter Reset Level LMTH ALC Limiter Detection Level 0 ADC Input 1 ADC Input Table 8. Auto Limiter Detection ...

Page 27

ASAHI KASEI Addr Register Name 05H ALC Mode Control 2 R/W Default REF6-0: Set the Reference value at ALC Recovery Operation During the ALC recovery operation, when IPGA value becomes the reference value set by REF6-0, the gain of the ...

Page 28

ASAHI KASEI Addr Register Name 06H Operation Mode R/W Default ALC: ALC Enable Flag 0: ALC Disable (Default) 1: ALC Enable FDOUT: FADEOUT Enable Flag 0: FADEOUT Disable (Default) 1: FADEOUT Enable FDIN: FADEIN Enable Flag 0: FADEIN Disable (Default) ...

Page 29

ASAHI KASEI Addr Register Name 07H Input PGA Control R/W Default IPGA6-0: Input Analog PGA; 97 levels; Commonly Lch and Rch of IPGA. The IPGA value should be the same or smaller than REF value before the ALC operation including ...

Page 30

ASAHI KASEI Figure 18 shows the system connection diagram. An evaluation board (AKD4565) is available which demonstrates the application circuit, the optimum layout, power supply arrangements and measurement results 0.1 ...

Page 31

ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4565 requires careful attention to power supply and grounding arrangements usually supplied from analog supply in system and VD is supplied from analog supply in system via a resistor ...

Page 32

ASAHI KASEI 28pin VSOP (Unit: mm) 9.8 0.2 0.65 +0.10 0.22 -0.05 0.12 M *1: Dimension does not include mold flash. n Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0132-E-01 ...

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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0132-E-01 MARKING AKM AK4565VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB : Lot number (X : Digit number Alpha character) ...

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