HYB18TC1G800BF-3S QIMONDA Qimonda AG, HYB18TC1G800BF-3S Datasheet
HYB18TC1G800BF-3S
Available stocks
Related parts for HYB18TC1G800BF-3S
HYB18TC1G800BF-3S Summary of contents
Page 1
...
Page 2
HYB18TC1G800AF, HYB18TC1G160AF Revision History: 2006-09, Rev. 1.11 Page Subjects (major changes since last revision) All Qimonda update All Adapted internet edition 102 Modified AC Timing Parameters Previous Revision: 2006-07, Rev. 1.1 Added more speedsorts: HYB18TC1G800AF-5, HYB18TC1G800AF-3.7, HYB18TC1G800AF-3S, HYB18TC1G160AF-5, HYB18TC1G160AF-3.7, HYB18TC1G160AF-3S ...
Page 3
Overview This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 1-Gbit Double-data-Rate SDRAM offers the following key features: ± ± • 1.8 V 0.1 V Power Supply 1.8 ...
Page 4
Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time Product Type Speed Code Speed Grade Max. Clock Frequency Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row ...
Page 5
... HYB18TC1G160BF–3.7 DDR2–533C ×8 HYB18TC1G800BF–3.7 DDR2–533C ×16 HYB18TC1G160BF–5 DDR2–400B ×8 HYB18TC1G800BF–5 DDR2–400B 1) CAS: Column Address Strobe 2) RCD: Row Column Delay 3) RP: Row Precharge Note: For product nomenclature see Chapter 9 Rev. 1.11, 2006-09 03292006-PJAE-UQLG CK falling). All I/Os are synchronized with a single ended ...
Page 6
Pin Configuration This chapter contains the pin configuration. 2.1 Pin Configuration for TFBGA–68 The pin configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 6 and Table 7 for ×8 components. Ball#/Pin# Name ...
Page 7
Ball#/Pin# Name Pin Type R8 A13 I NC – Data Signals ×8 Organizations G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 I/O F9 DQ7 I/O Data Strobe ×8 ...
Page 8
Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...
Page 9
Notes 1. RDQS / RDQS are enabled by EMRS(1) command RDQS / RDQS is enabled, the DM function is disabled Rev. 1.11, 2006-09 03292006-PJAE-UQLG Pin Configuration for ×8 components, P-TFBGA-68 (top view) 3. When enabled, RDQS & RDQS ...
Page 10
Pin Configuration for TFBGA-92 The pin configuration of a DDR2 SDRAM is listed by function in columns are explained in Table 9 and Table 10 for ×16 components. Ball#/Pin# Name Pin Type Clock Signals ×16 Organization ...
Page 11
Ball#/Pin# Name Pin Type Data Signals ×16 Organization G8 DQ0 I/O G2 DQ1 I/O H7 DQ2 I/O H3 DQ3 I/O H1 DQ4 I/O H9 DQ5 I/O F1 DQ6 I/O F9 DQ7 I/O C8 DQ8 I/O C2 DQ9 I/O D7 DQ10 ...
Page 12
Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NC Not Connected Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) LV-CMOS Low ...
Page 13
Notes 1. UDQS/UDQS is data strobe for upper byte, LDQS/LDQS is data strobe for lower byte Rev. 1.11, 2006-09 03292006-PJAE-UQLG Pin Configuration for ×16 components, P-TFBGA-92 (top view) 2. UDM is the data mask signal for the upper byte UDQ0~UDQ7, ...
Page 14
Functional Description This chapter describes the functional description. 1) Field Bits Type Description BA2 16 reg. addr. Bank Address [2] Note: BA2 not available on 256 Mbit and 512 Mbit components 0 B BA1 15 Bank Address [1] 0 ...
Page 15
Field Bits Type Description CL [6:4] w CAS Latency Note: All other bit combinations are illegal. 011 B 100 B 101 B 110 B 111 Burst Type [2:0] w Burst ...
Page 16
Field Bits Type Description A13 13 w Address Bus[13] Note: A13 is not available for 256 Mbit and 0 B Qoff 12 Output Disable RDQS 11 Read Data Strobe Output (RDQS, RDQS ...
Page 17
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 w Bank Address[2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0 BA2 Bank Address B BA [15:14] w Bank Adress[15:14] 00 ...
Page 18
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010 1) Field Bits Type Description BA2 16 reg.addr Bank Address[2] Note: BA2 is not available on 256 Mbit and 512 Mbit components 0 BA2 Bank Address B BA1 15 Bank Adress[1] 1 BA1 ...
Page 19
Input Pin ×8 components DQ[7:0] DQS DQS RDQS RDQS DM ×16 components DQ[7:0] DQ[15:8] LDQS LDQS UDQS UDQS LDM UDM Note don’t care bit set to low bit set to high Rev. 1.11, 2006-09 ...
Page 20
Burst Length Starting Address (A2 A1 A0) × × ×1 0 × ...
Page 21
Truth Tables The truth tables in this chapter summarize the commands and there signal coding to control a standard Double-Data-Rate-Two SDRAM. Function CKE Previous Cycle (Extended) Mode H Register Set Auto-Refresh H Self-Refresh Entry H Self-Refresh Exit L Single ...
Page 22
Current State CKE 6) Previous Cycle (N-1) Power-Down L L Self Refresh L L Bank(s) Active H All Banks Idle H H Any State other H than listed above 1) Current state is the state of the DDR2 SDRAM ...
Page 23
Operating Conditions This chapter lists the electrical distinguishes between abolute maximum ratings, DC 5.1 Absolute Maximum Ratings Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Symbol Parameter V V Voltage on pin ...
Page 24
DC Characteristics This chapter describes the DC characteristics. Symbol Parameter V Supply Voltage DD V Supply Voltage for DLL DDDL V Supply Voltage for Output DDQ V Input Reference Voltage REF V Termination Voltage ...
Page 25
DC & AC Characteristics DDR2 SDRAM pin timing are specified for either single ended or differential mode depending on the setting of the EMRS(1) “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The ...
Page 26
Symbol Parameter V DC input signal voltage IN(dc differential input voltage ID(dc differential input voltage ID(ac differential cross point input voltage IX(ac differential cross point output voltage 0.5 × OX(ac ...
Page 27
VTR VCP 5.4 Output Buffer Characteristics This chapter describes the Output Buffer Characteristics. Symbol Parameter I Output Minimum Source DC Current OH I Output Minimum Sink DC Current 1 1.42 V. ...
Page 28
Symbol Description — Output Impedance — Pull-up / Pull down mismatch — Output Impedance step size for OCD calibration S Output Slew Rate OUT Absolute Specifications ( ; = 1.8 V OPER DD meet timing, voltage and ...
Page 29
Overshoot and Undershoot Specification AC Overshoot / Undershoot Specification for Address and Control Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DD V Maximum undershoot area ...
Page 30
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area Maximum peak amplitude allowed for undershoot area V Maximum overshoot area above DDQ V Maximum undershoot area below SSQ AC ...
Page 31
Currents Specifications and Conditions For Double-Data-Rate-Two SDRAMs described in this data I sheet the maximum values are listed measurement conditions for characteristics are listed in DD Parameter Operating Current - One bank Active - Precharge t ...
Page 32
Parameter Distributed Refresh Current Refresh command every CK CK(IDD) valid commands, Other control and address inputs are switching, Data bus inputs are switching. Self-Refresh Current CKE ≤ 0.2 V; external clock off, CK and CK ...
Page 33
Symbol –3S DDR2–667D I 81 DD0 90 I 100 DD1 109 I 60 DD2N I 7 DD2P I 39 DD2Q I 65 DD3N I 22 DD3P 9 I 200 DD4R 240 I 200 DD4W 260 I 200 DD5B I 10 ...
Page 34
Timing Characteristics This chapter contains speed grade definition, AC timing parameter and ODT tables. 7.1 Speed Grade Definitions All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications ( List of Speed Grade Definition tables: • Table 37 ...
Page 35
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...
Page 36
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time 1) Timings are guaranteed with CK/CK differential Slew ...
Page 37
AC Timing Parameters List of Timing Parameters Tables. • Table 40 “Timing Parameter by Speed Grade - DDR2–667” on Page 37 • Table 41 “Timing Parameter by Speed Grade - DDR2–533” on Page 42 • Table 42 “Timing Parameter ...
Page 38
Parameter Active to active command period for 1KB page size products Active to active command period for 2KB page size products Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS ...
Page 39
The output timing reference voltage level New units, ‘ ‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘ CK.AVG under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual ...
Page 40
When the device is operated with input clock jitter, this parameter needs to be derated by the actual deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t t ...
Page 41
T1 T2 tHZ,tRPST CK CK Rev. 1.11, 2006-09 03292006-PJAE-UQLG Method for calculating transitions and endpoint VOH - x mV VTT + 2x mV VOH - 2x mV VTT + x mV VOL + 2x mV VTT ...
Page 42
Parameter DQ output access time from CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks ...
Page 43
Parameter Data hold skew factor Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Internal Read to ...
Page 44
The , and , parameters are referenced to a specific voltage level, which specify when the device output is no longer driving HZ RPST LZ RPRE begins ...
Page 45
Parameter DQS falling edge hold time from CK (write cycle) DQS falling edge to CK setup time (write cycle) Four Activate Window period Clock half period Data-out high-impedance time from Address and control input hold time Address ...
Page 46
Parameter Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command = 1.8 V ± 0 1.8 V ±0.1 V. See notes DDQ DD 2) Timing that is not specified is illegal and after such ...
Page 47
ODT AC Electrical Characteristics This chapter describes the ODT AC electrical characteristics. Symbol Parameter / Condition t ODT turn-on delay AOND t ODT turn-on AON t ODT turn-on (Power-Down Modes) AONPD t ODT turn-off delay AOFD t ODT turn-off ...
Page 48
Package Dimensions The 1-Gbit DDR2 SDRAM is sold in two different packages depending on the number of I/Os. Rev. 1.11, 2006-09 03292006-PJAE-UQLG HYB18TC1G[80/16]0AF Package Outline PG-TFBGA-68 48 Internet Data Sheet 1-Gbit DDR2 SDRAM FIGURE 10 ...
Page 49
Rev. 1.11, 2006-09 03292006-PJAE-UQLG HYB18TC1G[80/16]0AF Package Pinout P-TFBGA-92 (top view) 49 Internet Data Sheet 1-Gbit DDR2 SDRAM FIGURE 11 ...
Page 50
Product Nomenclature For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter. Example for Field Number 1 2 DDR2 DRAM HYB 18 Field Description 1 QIMONDA Component Prefix 2 Interface Voltage [V] 3 DRAM Technology, consumer variant ...
Page 51
List of Figures Pin Configuration for ×8 components, P-TFBGA-68 (top view ...
Page 52
List of Tables Table 1 Performance table for – ...
Page 53
Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 54
Edition 2006-09 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 München, Germany © Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or ...