DM9161E ETC ETC, DM9161E Datasheet
DM9161E
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DM9161E Summary of contents
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General Description The DM9161 is a physical layer, single-chip, and low power transceiver for 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast ...
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Table of Contents 1. General Description ..............................................3 2. Block Diagram ......................................................3 3. Features................................................................4 4. Pin Configuration: DM9161 LQFP ........................5 5. Pin Description......................................................6 5.1 Normal MII Interface, 21 pins..............................6 5.2 Media Interface, 4 pins........................................8 5.3 LED Interface, 3 pins ..........................................8 5.4 ...
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MII 10Base-T Nibble Transmit Timing Parameters ..................................................36 9.4.11 MII 10Base-T Nibble Transmit Timing Diagram........................................................36 9.4.12 MII 10Base-T Receive Nibble Timing Parameters .................................................. 37 9.4.13 MII 10Base-T Receive Nibble Timing Diagram........................................................37 9.4.14 Auto-negotiation and Fast Link Pulse Timing Parameters ..................................................37 ...
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Features Fully complies with IEEE 802.3u 10Base-T/100Base- TX Comply with ANSI X3T12 TP-PMD 1995 standard Support Auto-Negotiation function, compliant with IEEE 802.3u Fully integrated Physical layer single chip with direct interface to magnetic Integrated 10Base-T and 100Base-TX transceiver On-chip ...
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Pin Configuration: DM9161 LQFP RXDV/TESTMODE 37 RXER/RXD[4]/RPTR 38 DVDD 39 RESET# 40 DVDD 41 XT2 42 XT1 43 DGND AGND 46 BGRESG 47 BGRES 48 Final Version: DM9161-DS-F02 May 10,2002 10/100 Mbps Fast Ethernet Physical Layer ...
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Pin Description I: Input, O: Output, LI: Latch input when power-up/reset, Z: Tri-State output, U: Pulled up D: Pulled down 5.1 Normal MII Interface, 21 pins Pin No. Pin Name 16 TXER/TXD [4] 20,19,18,17 TXD [0:3] 21 TXEN 22 ...
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RXCLK /SCRAMEN /10BTSER 35 CRS /PHYAD[4] 36 COL /RMII 37 RXDV /TESTMODE 38 RXER/RXD[4] /RPTR 31 RXEN 40 RESET# Final Version: DM9161-DS-F02 May 10,2002 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver O, Receive Clock Z, The received ...
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Media Interface, 4 pins Pin No. Pin Name 3,4 RX+ RX- 7,8 TX+ TX- 5.3 LED Interface, 3 pins Pin No. Pin Name 11 FDX /COL LED# /OP0 12 SPEED LED# /OP1 13 LINK /ACT LED# /OP2 5.4 Mode, ...
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CABLESTS /LINKSTS 5.5 Bias and Clock, 4 pins Pin No. Pin Name 47 BGRESG 48 BGRES 42 XT2 43 XT1 5.6 Power, 13 pins Pin No. Pin Name 1,2 AVDD 9 AVDD 5 AGND 6 AGND 46 AGND 23,30,39,41 ...
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Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode Normal MII Mode TXD [0:1] TXD [2:3] TXEN TXER/TXD [4] TXCLK RXD [0:1] RXD[2:3] RXEN RXER/RXD[4]/RPTR/NODE RXDV RXCLK COL CRS (PHYADR [2:4]) (BP4B5B) MDC MDIO RESET# XT1 ...
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LED Configuration LEDs flash once per 500ms after power-on reset or software reset by writing PHY register. All LED pins are dual function pins, which can be configured as either active high or low by pulling them low or ...
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Functional Description The DM9161 Fast Ethernet single chip transceiver, providing the functionality as specified in IEEE 802.3u, integrates a complete 100Base-TX module and a complete 10Base-T module. The DM9161 provides a Media Independent Interface (MII) as defined in the ...
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MII Interface (continued) TXER (transmit coding error) synchronously with respect to TXCLK. If TXER is asserted for one or more clock periods, and TXEN is asserted, the PHY will emit one or more symbols that are not part of the ...
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Operation The 100Base-TX transmitter receives 4-bit nibble data clocked in at 25MHz at the MII, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts the 25MHz clock into a ...
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The block diagram in figure 7-3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI ...
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Code Group Symbol 10/100 Mbps ...
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Binary In Binary MLT-3 7.2.2 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data, which is then provided to the MII. The receive section contains ...
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Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized clock and data are ...
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Auto-Negotiation (continued) Auto-negotiation also provides a parallel detection function for devices that do not support the Auto- negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined discovered that ...
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Power Reduced Mode The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable disconnection,, DM9161 will automatically turn off the power and enter the Power Reduced mode, ...
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MII Register Description ADD Name CONTROL Reset Loop Speed back select 01 STATUS T4 TX FDX TX HDX Cap. Cap. Cap. 02 PHYID1 PHYID2 Auto-Neg. Next FLP ...
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Basic Mode Control Register (BMCR Bit Bit Name 0.15 Reset 0, RW/SC Reset 0.14 Loopback 0.13 Speed selection 0.12 Auto-negotiation enable 0.11 Power down 0.10 Isolate 0.9 Restart 0,RW/SC Restart Auto-negotiation Auto-negotiation 22 10/100 Mbps Fast Ethernet ...
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Duplex mode 0.7 Collision test 0.6-0.0 Reserved 8.2 Basic Mode Status Register (BMSR Bit Bit Name Default 1.15 100BASE-T4 0,RO/P 1.14 100BASE-TX 1,RO/P full-duplex 1.13 100BASE-TX 1,RO/P half-duplex 1.12 10BASE-T 1,RO/P full-duplex 1.11 10BASE-T 1,RO/P half-duplex 1.10-1.7 ...
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Jabber detect 0, RO/LH 1.0 Extended capability 8.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9161. The Identifier consists of a concatenation of ...
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Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9161 device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name Default 4.15 NP 0,RO/P 4.14 ACK 4.13 RF 4.12-4.11 ...
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Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12-5.11 Reserved 5.10 FCS 5.9 T4 5.8 TX_FDX ...
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Auto-negotiation Expansion Register (ANER)- 06 6.15-6.5 Reserved 6.4 PDF 0, RO/LH 6.3 LP_NP_ABLE 6.2 NP_ABLE 0,RO/P 6.1 PAGE_RX 0, RO/LH 6.0 LP_AN_ABLE 8.8 DAVICOM Specified Configuration Register (DSCR Bit Bit Name Default 16.15 BP_4B5B 16.14 BP_SCR 16.13 ...
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F_LINK_100 16.6 SPLED_CTL 16.5 COLLED_CTL 16.4 RPDCTR-EN 16.3 SMRST 16.2 MFPSC 16.1 SLEEP 16.0 RLOUT 28 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver latched into this bit at power-up/reset 0 = Normal MII 1 = Enable Reduced ...
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DAVICOM Specified Configuration and Status Register (DSCSR Bit Bit Name Default 17.15 100FDX 17.14 100HDX 17.13 10FDX 17.12 10HDX 17.11- Reserved 17.9 17.8-17.4 PHYADR[4:0] (PHYADR), 17.3-17.0 ANMB[3:0] Final Version: DM9161-DS-F02 May 10,2002 10/100 Mbps Fast Ethernet Physical ...
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Configuration/Status (10BTCSR Bit Bit Name 18.15 Reserved 18.14 LP_EN 18.13 HBE 18.12 SQUELCH 18.11 JABEN 18.10 10BT_SER 18.9-18.1 Reserved 18.0 POLR 8.11 DAVICOM Specified Interrupt Register – 21 Bit Bit Name 21.15 INTR PEND 21.14- Reserved ...
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INTR mask 21.7-21.5 Reserved 21.4 FDX change 0,RO/LH 21.3 SPD change 0, RO/LH 21.2 LINK change 0, RO/LH 21.1 Reserved 21.0 INTR status 0, RO/LH 8.12 DAVICOM Specified Receive Error Counter Register (RECR) – 22 Bit Bit Name Default ...
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LH_PH3 2 LH_PH2 1 LH_PH1 0 LH_PH0 9. DC and AC Electrical Characteristics 9.1 Absolute Maximum Ratings ( Symbol D A Supply Voltage VDD, VDD V DC Input Voltage ( Output Voltage(V OUT ...
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DC Electrical Characteristics (DVDD = 3.3V) Symbol Parameter TTL Inputs (TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, PHYAD0~4, OPMODE0-2, RPTR, BP4B5B, RESET Input Low Voltage IL V Input High Voltage IH I Input Low Leakage ...
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MDC/MDIO Timing Symbol Parameter t MDC Cycle Time 0 t1 MDIO Setup Before MDC t2 MDIO Hold After MDC t3 MDC To MDIO Output Delay 9.4.4 MDIO Timing When OUTPUT by STA MDC MDIO 9.4.5 MDIO Timing When OUTPUT ...
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Transmit Timing Parameters Symbol Parameter t TXCLK Cycle Time TXc TXCLK High/Low Time TXh TXl t TXD [0:3], TXEN, TXER Setup To TXCLK High TXD [0:3], TXEN, TXER Hold From TXCLK TX ...
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MII 100BASE-TX Receive Timing Diagram RXCLK RXD [0:3], RXDV, RXER CRS RX+/- COL 9.4.10 MII 10BASE-T Nibble Transmit Timing Parameters Symbol t TXD[0:3), TXEN, TXER Setup To TXCLK High TXD[0:3], TXEN, TXER Hold From TXCLK High ...
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MII 10BASE-T Receive Nibble Timing Parameters Symbol t RXD [0:3), RXDV, RXER Setup To RXCLK High RXD [0:3], RXDV, RXER Hold From RXCLK High RXI In To RXD [0:3] Out (Rx Latency) RX ...
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Clock Pulse FAST LINK PULSES FLP Burst FLP Bursts 9.4.16 RMII Receive Timing Diagram 9.4.17 RMII Transmit Timing Diagram 38 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Data Pulse ...
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RMII Timing Diagram REF_CLK TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER 9.4.19 RMII Timing Parameter Symbol REF_CLK Frequency REF_CLK Duty Cycle Tsu TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data Setup to REF_CLK rising edge Thold TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data hold ...
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Application Notes 10.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9161 RX± and TX± pins. Traces routed from RX± and ...
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RX+ 50Ω RX- 50Ω 1% DM9161 78Ω TX+ 78Ω TX- 47 BGRESG 48 BGRES Final Version: DM9161-DS-F02 May 10,2002 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Transformer 1:1 0.1µ F AGND ...
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Power Decoupling Capacitors Davicom Semiconductor recommends that all the decoupling capacitors of all power supply pins are placed as close as possible to the power pads of the DM9161 (The DVDD DVDD 42 10/100 Mbps Fast Ethernet Physical Layer ...
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Ground Plane Layout A single ground plane approach is recommended to minimize EMI. Bad ground plane partitioning can cause more EMI emissions that could make the network interface Final Version: DM9161-DS-F02 May 10,2002 10/100 Mbps Fast Ethernet Physical Layer ...
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Power Plane Partitioning The power planes should be approximately illustrated in Figure 10-5. The ferrite bead used should have an impedance at least 75Ω at 100MHz. A suitable bead is the Panasonic surface mound 44 10/100 Mbps Fast Ethernet ...
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Magnetics Selection Guide Refer to Table 10-2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should Manufacturer Pulse Engineering Delta YCL Halo Nano Pulse Inc. Fil-Mag Bel Fuse Valor Macronics 10.8 ...
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Package Information LQFP 48L (F.P. 2mm) Outline Dimensions Symbol Dimensions in inches Min. Nom. Max 0.063 A1 0.002 - 0.006 A2 0.053 0.055 0.057 b 0.007 0.009 0.011 b1 0.007 0.008 0.009 C 0.004 - 0.008 ...
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... Order Information Part Number Pin Count DM9161E 48 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold Semiconductor are covered by the warranty and patent indemnification, and the provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement ...