ADSP2183 ADI, ADSP2183 Datasheet
ADSP2183
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ADSP2183 Summary of contents
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ICE-Port is a trademark of Analog Devices, Inc. DSP Microcomputer FUNCTIONAL BLOCK DIAGRAM POWERDOWN CONTROL MEMORY DATA ADDRESS PROGRAM GENERATORS PROGRAM SEQUENCER MEMORY MEMORY DAG 1 DAG 2 PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY ...
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ADSP-2183 This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • ...
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In addition to the address and data bus for external memory connection, the ADSP-2183 has a 16-bit Internal DMA port (IDMA port) for connection to external systems. The IDMA port is made data/address pins and five control ...
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ADSP-2183 • SPORTs support serial data word lengths from bits and provide optional A-law and µ-law companding according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word ...
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Table I. Interrupt Priority and Interrupt Vector Addresses Interrupt Vector Source of Interrupt Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Power-Down (Nonmaskable) 002C IRQ2 0004 IRQL1 0008 IRQL0 000C SPORT0 Transmit 0010 SPORT0 Receive 0014 IRQE 0018 ...
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... MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting (MMAP = 0), the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. ...
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Memory Architecture The ADSP-2183 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O. Program Memory is a 24-bit-wide space for storing both instruction opcodes and data. The ...
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... BMWAIT register. Byte Memory DMA (BDMA) The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space, while the processor is operating normally and steals only one DSP cycle per 8-, 16- or 24-bit word transferred ...
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... Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Bootstrap Loading (Booting) The ADSP-2183 has two mechanisms to allow automatic load- ing of the on-chip program memory after reset. The method for booting after reset is controlled by the MMAP and BMODE pins as shown in Table VI ...
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ADSP-2183 If Go Mode is enabled, the ADSP-2183 will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2183 is performing an external memory access when the external device asserts the BR ...
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... RAM), all sections of your executable mapped into boot pages are not loaded. Write your target architecture file to indicate that only PM RAM is available for program storage, when using the EZ-ICE software’s loading feature. Data can be loaded to PM RAM or DM RAM. ADSP-2183 ...
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ADSP-2183–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS Parameter V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter V Hi-Level Input Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level Output Voltage OL I Hi-Level Input ...
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... ESD SENSITIVITY ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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ADSP-2183 Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High ...
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Parameter Bus Request–Bus Grant Timing Requirements: BR Hold after CLKOUT High Setup before CLKOUT Low t BS Switching Characteristics: CLKOUT High to xMS RD, WR Disable xMS, RD SDB Disable to BG Low ...
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ADSP-2183 Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD ...
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Parameter Memory Write Switching Characteristics: Data Setup before WR High t DW Data Hold after WR High Pulsewidth Low to Data Enabled t WDE A0–A13, xMS Setup before WR Low t ASW Data Disable ...
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ADSP-2183 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High ...
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Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA t ...
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ADSP-2183 Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of ...
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Parameter IDMA Write, Long Write Cycle Timing Requirements: IACK Low before Start of Write t IKW IAD15–0 Data Setup before IACK Low t IKSU IAD15–0 Data Hold after IACK Low t IKH Switching Characteristics: Start of Write to IACK Low ...
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ADSP-2183 Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Setup before IACK Low IKDS ...
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Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read IKDH ...
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ADSP-2183 OUTPUT DRIVE CURRENTS Figure 19 shows typical I-V characteristics for the output drivers of the ADSP-2183. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 ° 3.6V, ...
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... CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2183 + 3. 100 120 C – NOMINAL –2 –4 – 120 C – TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...
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ADSP-2183 IAL 1 PIN 1 PF3 2 IDENTIFIER PF2 3 PF1 4 PF0 IOMS 8 BMS 9 DMS 10 CMS 11 GND PMS ...
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LQFP Pin LQFP Number Name Number 1 IAL 33 2 PF3 34 3 PF2 35 4 PF1 36 5 PF0 IOMS 8 40 BMS 9 41 DMS 10 42 CMS ...
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ADSP-2183 IWR GND GND IRD D21 D23 D17 D20 D22 GND D15 D18 D14 GND VDD D10 D11 D13 GND D2 GND VDD VDD D1 EBG BR EBR EINT ELOUT ELIN EMS ECLK EE ...
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Ball # Name Ball # A01 IAL D01 IS A02 D02 A03 GND D03 A04 PF6 D04 A05 IAD2 D05 A06 GND D06 A07 IAD6 D07 A08 IAD10 D08 A09 IAD14 D09 IWR A10 D10 A11 GND D11 A12 GND ...
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ADSP-2183 128-Lead Metric Plastic Thin Quad Flatpack (LQFP) 0.75 (0.030) 0.60 (0.024) 0.50 (0.020) SEATING 0.08 (0.003) MAX LEAD COPLANARITY 0.15 (0.006) 0.05 (0.002) OUTLINE DIMENSIONS Dimensions given in mm and (inches). (ST-128) 16.20 (0.638) 16.00 (0.630) 1.60 (0.063) 15.80 ...
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SQ 0.384 (9.75) 0.067 (1.70) MAX NOTE THE ACTUAL POSITION OF THE BALL POPULATION IS WITHIN 0.006 (0.150) OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.003 ...