A1020B

Manufacturer Part NumberA1020B
ManufacturerActel Corporation
A1020B datasheet
 


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ACT Timing Char act er i st i cs

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ACT 1 Timing Char act er i st i cs
(Worst-Case Commercial Conditions)
Input Module Propagation Delays
Parameter Description
t
Pad to Y High
INYH
t
Pad to Y Low
INYL
Input Module Predicted Routing Delays
t
FO=1 Routing Delay
IRD1
t
FO=2 Routing Delay
IRD2
t
FO=3 Routing Delay
IRD3
t
FO=4 Routing Delay
IRD4
t
FO=8 Routing Delay
IRD8
Global Clock Network
t
Input Low to High
CKH
t
Input High to Low
CKL
t
Minimum Pulse Width
PWH
High
t
Minimum Pulse Width
PWL
Low
t
Maximum Skew
CKSW
t
Minimum Period
P
f
Maximum Frequency
MAX
Note:
1.
These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
1-298
(continued)
‘–3’ Speed
‘–2’ Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
3.1
3.5
3.1
3.5
1
0.9
1.1
1.4
1.7
2.1
2.5
3.1
3.6
6.6
7.7
FO = 16
4.9
5.6
FO = 128
5.6
6.4
FO = 16
6.4
7.4
FO = 128
7.0
8.1
FO = 16
6.5
7.5
FO = 128
6.8
8.0
FO = 16
6.5
7.5
FO = 128
6.8
8.0
FO = 16
1.2
1.3
FO = 128
1.8
2.1
FO = 16
13.2
15.4
FO = 128
14.2
16.7
FO = 16
75
65
FO = 128
70
60
‘–1’ Speed ‘Std’ Speed 3.3 V Speed
4.0
4.7
6.8
4.0
4.7
6.8
1.2
1.4
2.0
1.9
2.2
3.2
2.8
3.3
4.8
4.1
4.8
7.0
8.7
10.2
14.8
6.4
7.5
6.7
7.3
8.6
7.9
8.4
9.9
8.8
9.2
10.8
10.0
8.5
10.0
8.9
9.0
10.5
9.8
8.5
10.0
8.9
9.0
10.5
9.8
1.5
1.8
1.5
2.4
2.8
2.4
17.6
20.9
18.2
18.9
22.3
20
57
48
55
53
45
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz