OV2610

Manufacturer Part NumberOV2610
DescriptionColor CMOS UXGA (2.0 MPixel) Camera Chip
ManufacturerOmniVision Technologies, Inc.
OV2610 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
Page 19/24:

Bit : Clock divider

Download datasheet (528Kb)Embed
PrevNext
O
mni
ision
Table 11
Device Control Register List
Address
Register
Default
(Hex)
Name
(Hex)
11
CLKRC
00
12
COMH
20
Version 1.4, September 15, 2003
R/W
Clock Rate Control
Bit[7]:
Internal PLL ON/OFF selection
0:
PLL disabled
1:
PLL enabled
Bit[6]:
Digital video port master/slave selection
RW
0:
Master mode, sensor provides PCLK
1:
Slave mode, external PCLK input from XCLK1 pin
Bit[5:0]: Clock divider
CLK = XCLK1/(decimal value of CLKRC[5:0] + 1)
Common Control H
Bit[7]:
SRST
1:
Initiates soft reset. All register are set to factory
default values after which the chip resumes normal
operation
Bit[6]:
Resolution selection
0:
UXGA
1:
SVGA
Bit[5]:
Average luminance value pixel counter ON/OFF
0:
OFF
1:
ON
Bit[4]:
Reserved
RW
Bit[3]:
Master/slave selection
0:
Master mode
1:
Slave mode
Bit[2]:
Window output selection
0:
Output only pixels defined by window registers
1:
Output all pixels
Bit[1]:
Color bar test pattern
0:
OFF
1:
ON
Bit[0]:
ADC mode selection
0:
2 channel ADC
1:
4 channel ADC
Proprietary to OmniVision Technologies
Register Set
Description
19