TDA3606AT/N1 QuickLogic, TDA3606AT/N1 Datasheet

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TDA3606AT/N1

Manufacturer Part Number
TDA3606AT/N1
Description
FPGA, pASIC 1 Family, Very-High-Speed CMOS FPGA
Manufacturer
QuickLogic
Datasheet

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usable ASIC gates,
192 Logic Cells
Block Diagram
HIGHLIGHTS
88 I/O pins
QL12x16B
…2,000
pASIC
Low-Power, High-Output Drive – Standby current typically 2
mA. A 16-bit counter operating at 100 MHz consumes less than 50
mA. Minimum IOL of 12 mA and IOH of 8 mA
Low-Cost, Easy-to-Use Design Tools
simulated using QuickLogic's new QuickWorks
environment, or with third-party CAE tools including Viewlogic,
Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place
and route on PC and workstation platforms using QuickLogic
software.
= Up to 80 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells
Very High Speed – ViaLink
antifuse technology, allows counter speeds over 150 MHz and logic
cell delays of under 2 ns.
High Usable Density
provides 2,000 usable ASIC gates (4,000 PLD gates) in 68-pin and
84-pin PLCC, 84-pin CPGA and 100-pin TQFP packages.
4-13
Very-High-Speed CMOS FPGA
A 12-by-16 array of 192 logic cells
metal-to-metal programmable–via
pASIC
Designs entered and
QL12X16B
®
1 Family
development
Rev C
4

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TDA3606AT/N1 Summary of contents

Page 1

... Low-Cost, Easy-to-Use Design Tools simulated using QuickLogic's new QuickWorks environment, or with third-party CAE tools including Viewlogic, Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place and route on PC and workstation platforms using QuickLogic software. QL12x16B Block Diagram 192 Logic Cells = prog ...

Page 2

... DSPs. Designs can be entered using QuickLogic’s QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software ...

Page 3

QL12x16B Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation. Pinout Diagram 68-pin PLCC Pinout Diagram 84-pin PLCC 4-15 4 ...

Page 4

Pinout Diagram 84-pin CPGA CPGA 84 Function/Connector Pin Table PIN FUNC PIN B10 A10 GND ...

Page 5

QL12x16B Pinout Diagram 100-pin TQFP 4-17 4 ...

Page 6

ABSOLUTE MAXIMUM RATINGS Supply Voltage ................................. –0.5 to 7.0V Input Voltage ....................... –0.5 to VCC +0.5V ESD Pad Protection .................................. ±2000V DC Input Current...................................... ±20 mA Latch-up Immunity................................. ±200 mA OPERATING RANGE Symbol Parameter VCC Supply Voltage TA Ambient Temperature ...

Page 7

QL12x16B AC CHARACTERISTICS at VCC = 5V 25° 1.00) Logic Cell Symbol tPD Combinatorial Delay [5] tSU Setup Time [5] tH Hold Time tCLK Clock to Q Delay tCWHI Clock High Time tCWLO Clock Low Time ...

Page 8

... ORDERING INFORMATION pASIC device part number B = 0.65 micron CMOS Clock Drivers Wired Together 12x16B - 1 PF100 C QuickLogic pASIC device prefix Speed Grade X = quick 0 = fast 1 = faster 2 = fastest 4-20 QL12x16B Propagation Delays (ns) [4] Fanout 4.5 5 ...

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