CA91L862A-50CE Tundra Semiconductor, CA91L862A-50CE Datasheet
CA91L862A-50CE
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CA91L862A-50CE Summary of contents
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... QSpan II (CA91L862A) PCI-to-Motorola Processor Bridge Manual www.tundra.com ...
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... Tundra was negligent regarding the design or manufacture of the part. The acceptance of this document will be construed as an acceptance of the foregoing conditions. Product: QSpan II (CA91L862A) Title: QSpan II PCI-to-Motorola Processor Bridge Manual Document: 8091862.MA001.06 ...
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Revision History 8091862.MA001.06, Final Manual, September 2000 8091862.MA001.05, Final Manual, September 2000 8091862.MA001.04, Preliminary Manual, December 1999 8091862.MA001.03, Preliminary Manual, September 1999 8091862.MA001.02, Preliminary Manual, September 1999 8091862.MA001.01, Preliminary Manual, August 1999 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 3 ...
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Revision History 4 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Contents Chapter 1: General Information 1.1 ...
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Contents 3.2.1 QBus Slave Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Transaction Decoding ...
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Contents Chapter 5: The IDMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 8: The Interrupt Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.1 Overview . ...
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Contents Chapter 12: CompactPCI Hot Swap Friendly Support . . . . . . . . . . . . . . 149 12.1 Overview . . . . . . . . . . . . . . . ...
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Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents Appendix C: Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 C.1 MC68360 Interface . ...
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C.3.1.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents Appendix F: Operating and Storage Conditions . . . . . . . . . . . . . . . . . . 401 F.1 Power Dissipation . . . . . . . . . . . ...
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List of Figures Figure 1: QSpan II Bridging PCI and Processor Buses ...
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List of Figures Figure 28: Single Write — QSpan II as MC68360 Master . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 63: Single Write — QSpan II as M68040 Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures 18 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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List of Tables Table 1: QSpan II New Features and Functional Enhancements Table 2: ...
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List of Tables Table 29: M68040 Cycle Terminations of QBus Master Module . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table ...
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Table 63: Pin Assignments for Ground (V Table 64: No-connect Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 98: PCI Bus Address Error Log Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 133: QBus Slave Image 0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 168: PCI Bus Error Logging Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Corporate Profile Tundra Semiconductor Corporation Tundra Semiconductor Corporation (TSE:TUN) designs, develops, and markets advanced System Interconnect for use by the world's leading Internet and communications infrastructure vendors. Tundra chips provide the latest interface and throughput features to help these vendors design and deliver more powerful equipment in shorter timeframes ...
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... Tundra can anticipate and meet the future directions and needs of communications systems designers and manufacturers. Tundra Customers Tundra semiconductor products are used by the world's leading communications infrastructure vendors, including Cisco, Motorola, Ericsson, Nortel, Lucent, IBM, Xerox, Hewlett-Packard, 3Com, Nokia, Siemens, Newbridge, Alcatel, Matsushita, OKI, Fujitsu, Samsung, and LGS ...
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Chapter 1: General Information This chapter describes the main functions and features of the QSpan II. It also discusses general document elements and technical support information. The following topics are discussed: • “What is the QSpan II” on page 28 ...
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... Chapter 1: General Information 1.1 What is the QSpan II The QSpan II™ chip is a member of Tundra Semiconductor Corporation’s growing family of PCI bus-bridging devices. QSpan II enables board designers to bring PCI-based embedded products to market faster, for less cost, and with high performance. Developed as part of an ongoing strategic relationship with Motorola®, QSpan II is designed to gluelessly bridge the MC68360 (QUICC™ ...
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QSpan II Features QSpan II has the following features: • A direct-connect interface to the PCI bus for Motorola’s MC68360 and MPC860 communications controllers, and the M68040 Host processor. • QSpan compatible • Support for MHz ...
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Chapter 1: General Information 1.1.2 QSpan II verses QSpan The following table summarizes the main QSpan II features that were unavailable in the QSpan device. Table 1: QSpan II New Features and Functional Enhancements Description Features DMA Channel Vital Product ...
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Document Conventions 1.2.1 Signals Signals are either active high or active low. Active low signals are defined as true (asserted) when they are at a logic low. Similarly, active high signals are defined as true at a logic high. ...
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Chapter 1: General Information 1.2.5 Symbols This symbol directs the reader to useful information or suggestions. This symbol alerts the reader to procedures or operating levels which may result in misuse or damage to the product. This symbol alerts the ...
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Customer Support Information Tundra is dedicated to providing its customers with superior technical documentation and support. The following types of support are available: • QSpan II Web Page: This web page briefly describes QSpan II’s features, benefits, typical applications, ...
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Chapter 1: General Information 34 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Chapter 2: Functional Overview This chapter briefly discusses the main functional components (also referred to as channels) of the QSpan II. Please see the following chapters for a detailed explanation of each component: • Chapter 3: “The QBus Slave Channel” ...
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Chapter 2: Functional Overview Figure 2: QSpan II Functional Diagram PCI Interface PCI Master Module PCI Bus Arbiter PCI Bus CompactPCI Hot Swap PCI Target Module 2.2 The QBus Slave Channel The QBus Slave Channel transfers data between the QBus ...
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The PCI Target Channel The PCI Target Channel transfers data between the PCI bus and the QBus (see Figure 2). It supports posted writes — to ensure zero-wait state bursting — prefetched reads, and delayed single reads and writes. ...
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Chapter 2: Functional Overview PCI Configuration cycles can be generated from the QBus by accessing QSpan II registers. The cycles proceed as delayed transfers (for information, see Register Channel” on page 2.7 The Interrupt Channel QSpan II can generate interrupts ...
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Chapter 3: The QBus Slave Channel This chapter describes the QSpan II’s QBus Slave Channel. The following topics are discussed: • “QBus Slave Channel Architecture” on page 40 • “Channel Description” on page 42 • “Address Phase” on page 43 ...
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Chapter 3: The QBus Slave Channel Figure 3: QBus Slave Channel — Functional Diagram PCI Target PCI Bus 3.2 QBus Slave Channel Architecture Figure 3 shows the QBus Slave Channel in relation to the QBus and the PCI bus. The ...
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QBus Slave Module The QBus Slave Module is a non-multiplexed 32-bit address, 32-bit data interface. The QBus Slave Module accepts MC68360 cycles, and either MPC860 or M68040 cycles. The QBus Slave Module’s mode is set by the SIZ[1] signal ...
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Chapter 3: The QBus Slave Channel When the QBus Slave Module detects a parity error it sets the QDPE_S bit but continues the transfer as if there were no parity error. For example write is directed to the ...
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Address Phase 3.4.1 Transaction Decoding and QBus Slave Images QSpan II accepts a transaction through its QBus Slave Module when one of its chip selects is asserted along with the Address Strobe (AS_) or Transaction Start signal (TS_). The ...
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Chapter 3: The QBus Slave Channel The following tables summarize the QBus Slave Image control and address fields. Table 3: Address Fields for QBus Slave Image Field Block Size BS (Table 138 on page 291 and Table 145 on page ...
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MPC860 Cycles QSpan II behaves as an MPC860 slave in response to the assertion of the TS_ signal when it is powered- MPC860 slave (see When the QBus Slave Module receives TS_ it responds with DSACK1_/TA_, BERR/TEA_, ...
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Chapter 3: The QBus Slave Channel 3.4.2 PCI Bus Request The PCI Master Module requests the PCI bus when one of the following occurs: • write data is received in the Qx-FIFO • after the last data phase of a ...
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Figure 4: Address Generator for QBus Slave Channel Transfers Translation Address This manual adopts the convention that the most significant bit (address or data) is always the largest number. MPC860 designers must ensure that they connect their pins accordingly. For ...
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Chapter 3: The QBus Slave Channel Table 5: Translation of QBus Address to PCI Address BS in QBSI0_CTL or QBSI1_CTL Block Size 0000 0001 128 Kbytes 0010 256 Kbytes 0011 512 Kbytes 0100 0101 0110 0111 1000 1001 1010 1011 ...
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Address Phase on the PCI Bus The address supplied on the AD[31:0] lines on the PCI bus is the result of the address translation described in the previous section. The PCI command encoding on the C/BE#[3:0] lines is determined ...
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Chapter 3: The QBus Slave Channel PCI Targets are expected to assert DEVSEL# if they have decoded the access target does not respond with DEVSEL# within 6 clocks, a Master-Abort is generated by the QSpan II. The following ...
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The following tables describe cycle mapping for Little-Endian and Big-Endian of all sizes (8, 16, 24 bits). Table 8: Little-Endian QBus Slave Channel Cycle Mapping SIZ[1: ...
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Chapter 3: The QBus Slave Channel Table 9: Big-Endian QBus Slave Channel Cycle Mapping SIZ[1: 3.5.2 Data Path 3.5.2.1 Writes If the PWEN bit ...
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Posted write transfers are stored in the Qx-FIFO. Address and data are stored as separate entries in the Qx-FIFO. For example, one single cycle data beat transaction is stored as two Qx-FIFO entries: one entry for the address of the ...
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Chapter 3: The QBus Slave Channel 3.5.2.2 Read Transactions — Burst and Single Cycle During a read transaction, address, data, size and transaction code signals are latched by the QBus Slave Module. After latching the information, the QSpan II retries ...
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If the QSpan II detects a prefetchable cycle when it is active during an MPC860 IDMA transfer (DREQ_ asserted), it converts the prefetch cycle into a normal delayed read cycle because the DACK_ can be delayed with respect to TS_. ...
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Chapter 3: The QBus Slave Channel This feature improves system performance, especially when using the DMA and where strict transaction ordering is not required. 3.5.3 PCI Target Channel Reads In PCI Target Channel reads, the PCI Target Module latches the ...
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Termination Phase Except during posted writes, the termination generated by the QBus Slave Module is determined by the termination on the PCI bus (see page 59). For read transactions and delayed write transactions, the QBus master is retried until ...
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Chapter 3: The QBus Slave Channel • A delayed transfer or a prefetched read results in a Target-Abort and the MA_BE_D bit in the MISC_CTL register the MA_BE_D bit is 1 and the TA_BE_EN bit in the ...
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The following table summarizes the QSpan II’s response to abnormal terminations on the PCI bus. Table 14: QBus Slave Channel Error Responses Transfer- MA_BE_D in type PCI Error Type read Master-Abort Target-Abort posted Master-Abort write Target-Abort a. This column pertains ...
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Chapter 3: The QBus Slave Channel QSpan II can record the address, command, data, and byte enables of a posted write transaction that results in a Master-Abort or Target-Abort. The EN bit of the PB_ERRCS register enables error recording. If ...
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Chapter 4: The PCI Target Channel This chapter describes the QSpan II’s PCI Target Channel. The following topics are discussed: • “PCI Target Channel Architecture” on page 62 • “Channel Description” on page 64 • “Address Phase” on page 65 ...
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Chapter 4: The PCI Target Channel Figure 5: PCI Target Channel — Functional Diagram PCI Bus PCI Master (DMA) 4.2 PCI Target Channel Architecture Figure 5 shows the PCI Target Channel in relation to the QBus and the PCI bus. ...
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Px-FIFO and Pr-FIFO The Px-FIFO is a 256-byte buffer for posted writes from the PCI bus to the QBus. The Px-FIFO can accept data from a PCI master while writing data to a QBus slave (see “Posted Writes” on ...
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Chapter 4: The PCI Target Channel 4.2.3.1 QBus Data Parity Generation and Detection The QBus Master Module supports the generation and detection of QBus data parity. The use of QBus data parity is optional. The data parity is valid on ...
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Address Phase 4.4.1 Transaction Decoding All decoding by the PCI Target Module is based on the address and command information produced by a PCI bus master. The PCI Target Module claims a cycle if there is an address driven ...
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Chapter 4: The PCI Target Channel Table 16: Address Fields for PCI Target Image (Continued) Field PCI Address Space Memory space or I/O space (PAS) Translation Address Address bits that are substituted to (TA[31:16]) generate the QBus address Table 17: ...
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Table 17: Control Fields for PCI Target Image (Continued) Field Burst Write Enable Determines whether the QSpan II (BRSTWREN) burst writes data on the QBus Invert Endianness Determines whether the QSpan II (INVEND) inverts the endian setting of the QB_BOC ...
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Chapter 4: The PCI Target Channel A PCI Target Image occupies a range of addresses within PCI Memory or I/O space. The PCI Address Space bit determines whether the Target Image lies in PCI Memory or I/O space. The range ...
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Figure 6: Address Generator for PCI Target Channel Transfers Translation Address The Address Generator produces the QBus address using three inputs: the address generated by the PCI master (AD[31:0]), the block size of the PCI Target Image (BS field of ...
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Chapter 4: The PCI Target Channel Table 18: Translation of PCI Bus Address to QBus Address BS in PBTI0_CTL or PBTI1_CTL Block Size 0000 64 Kbytes 0001 128 Kbytes 0010 256 Kbytes 0011 512 Kbytes 0100 0101 2 Mbytes 0110 ...
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PCI BIOS Memory Allocation The PCI Target Image registers used by the QSpan II to decode PCI accesses work differently depending on the EEPROM implementation and the use of the PCI Access Disabled (PCI_DIS) bit in MISC_CTL2 (see Table ...
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Chapter 4: The PCI Target Channel When PCI address information is not loaded from an EEPROM or initiated by the processor on the QBus; the base address can only be set through the PBTIx_ADD registers. The PBTIx_ADD registers do not ...
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QBus Port Tables 19 and 20 describe write transfers of various sizes to 32-bit peripherals on the QBus. The following table describes mapping of 8, 16, and 32-bit write transfers through the PCI Target Channel with the QBus set ...
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Chapter 4: The PCI Target Channel 16-Bit QBus Port 16-bit QBus port transfers are explained in terms of the 32-bit transfers described in Tables 19 and 20. The first of these operations involves unpacking data. • A 32-bit write operation ...
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The following table describes mapping of 8-bit, 16-bit, and 32-bit read transfers through the PCI Target Channel in Little-Endian mode to 32-bit QBus peripherals. The byte-lane ordering is preserved in Little-Endian mode. Table 21: Little-Endian PCI Target Read Cycle Mapping ...
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Chapter 4: The PCI Target Channel 16-Bit QBus Port Tables 23 and 24 describe 8-bit and 16-bit read transfers from 16-bit QBus peripherals. The following table describes mapping of 8-bit and 16-bit read transfers through the PCI Target Channel in ...
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A 32-bit read operation from a peripheral with a 16-bit QBus port size is performed as two 16-bit read operations from a peripheral with a 16-bit QBus port size. 8-Bit QBus Port The following table describes mapping of 8-bit read ...
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Chapter 4: The PCI Target Channel 4.5.2 Data Path This section explains how data flows between the PCI bus and the QBus through the PCI Target Channel. 4.5.2.1 Posted Writes If the Posted Write Enable (PWEN) bit in the Target ...
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The Px-FIFO stores the address and data entries of PCI bursts. For example burst of four is received by the PCI Target Module, the QSpan II stores the burst as five new entries of the following types: address, ...
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Chapter 4: The PCI Target Channel 4.5.2.3 Single Read Transactions When the QSpan II receives a target read request, it latches the address and C/BE# information and retries the PCI master. QSpan II then becomes QBus master and initiates a ...
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Parity Monitoring by PCI Target Module The PCI Target Module monitors parity during the address phase of transactions and during the data phase of write transfers. For example, the QSpan II compares the PAR signal with the parity of ...
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Chapter 4: The PCI Target Channel 4. The QBus Master Module completes the read on the QBus. 5. The QBus Slave Module retries all non-register accesses. 6. The Qx-FIFO is emptied. 7. The PCI Target Module allows the read to ...
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QSpan II can operate synchronously because all timing parameters can be met by the MC68360. However, the MC68360 must be programmed for asynchronous mode in order for the QSpan II to meet the MC68360’s input setup requirements. See Appendix B: ...
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Chapter 4: The PCI Target Channel 4.7.3 M68040 Bus Arbitration When the QSpan II requires control of the M68040 bus, it arbitrates for the bus by asserting BR_. When the QSpan II samples BG_ asserted and BB_/BGACK_ negated, the QSpan ...
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Table 27: MC68360 Cycle Terminations of QBus Master Module DSACK0_, DSACK1_/TA_ Termination t Type 0 Normal Asserted a Normal & Halt Asserted Bus Error Don’t Care Don’t Care Retry Don’t Care Don’t Care t : First sample on falling edge ...
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Chapter 4: The PCI Target Channel 4.8.5 Terminations driven by the PCI Target Module This section lists the terminations generated by the PCI Target Module, and summarizes the conditions under which the various terminations are issued. Under most conditions, the ...
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Target-Retry During a Target-Retry, a termination is requested by the target because it cannot currently process the transaction. This termination is communicated by the target asserting STOP# while not asserting TRDY#. Target-Retry means that the transaction is terminated after ...
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Chapter 4: The PCI Target Channel Table 30: Translation of Cycle Termination QBus Termination Received Bus Error a. This table applies to read transactions and delayed write transactions. b. This cycle is not translated. The PCI Target Module retries the ...
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...
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Chapter 5: The IDMA Channel Figure 7: IDMA Channel — Functional Diagram PCI Interface PCI Master Module PCI Bus PCI Target Module The IDMA Channel contains a bi-directional 256-byte (64-entry deep) FIFO called I-FIFO. IDMA transactions are initiated on the ...
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QSpan II can be programmed to operate as a QBus IDMA peripheral. Although the QBus Master and Slave mode is determined at reset, this does not affect the QBus Slave Module which dynamically accepts MC68360 (QUICC) or MPC860 (PowerQUICC) IDMA ...
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Chapter 5: The IDMA Channel • The CMD bit in the IDMA/DMA_CS register determines whether the read transaction on PCI proceeds as a Memory Read Line transaction or a Memory Read Multiple transaction (see Table 109 on page 252). • ...
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PCI Write Transactions This section describes the operation and programming of the QSpan II to move data from the QBus to the PCI bus using the MC68360 or MPC860 IDMA. IDMA registers need to be programmed for a write ...
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Chapter 5: The IDMA Channel QSpan II requests the PCI bus when there is as much data in the I-FIFO as is specified by the IWM field of the IDMA/DMA_CS register (if the IWM equals 0, the QSpan II requests ...
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IDMA Status Tracking The following bits in the IDMA/DMA_CS register record the status of the transaction: • The IDMA/DMA Active Status (ACT) bit in the IDMA/DMA_CS is set by the QSpan II to indicate that an IDMA transfer is ...
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Chapter 5: The IDMA Channel Table 31: QSpan II’s Response to IDMA Errors PCI Bus PCI Bus Error Transfer Prefetching stops. IPE is set in the IDMA/DMA_CS register. Then the QSpan II negates DREQ_. If Read enabled, an interrupt is ...
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An IDMA transfer that is halted due to an IDMA error (IPE or IQE asserted), will not resume once the error condition is cleared. The IDMA Channel needs to be reset by setting the IRST_REQ bit of the IDMA/DMA_CS (see ...
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Chapter 5: The IDMA Channel Table 33: 16-Bit Little Endian IDMA Cycle Mapping QBus Timing SIZ[1:0] 10 First 16-bit transfer: 10 Second 16-bit transfer: The following table describes mapping of 16-bit QBus transactions in Big-Endian mode. The addressing of bytes ...
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Chapter 6: The DMA Channel This chapter examines the function of the QSpan II’s DMA Channel. The following topics are discussed: • “DMA Registers” on page 101 • “Direct Mode DMA Operation” on page 103 • “Linked List Mode DMA ...
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Chapter 6: The DMA Channel Figure 8: DMA Channel — Functional Diagram PCI Interface PCI Master Module PCI Bus PCI Target Module There are two modes of operation for the DMA Channel: Direct Mode and Linked List Mode (also called ...
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DMA Registers The DMA Channel uses the IDMA registers (starting at Register offset 400), as well as three additional registers: DMA_QADD (see Table 113 on page The PCI address for the DMA transfer resides in IDMA/DMA Address Register (IDMA/DMA_PADD). ...
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Chapter 6: The DMA Channel The three fields described in the previous paragraph are similar to the fields of the same name in PCI Target Image registers (PBTIx_CTL). The IWM field controls the burst size on PCI. If the IWM ...
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The KEEP_BB bit in the MISC_CTL2 register (see page when the QSpan II DMA channel is used with the PowerQUICC memory controller (UPM). 6.2.2 DMA Cycles on QBus QSpan II can limit the number of single reads and writes performed ...
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Chapter 6: The DMA Channel QSpan II initiates read transfers on the source bus to fill the I-FIFO. Once data is available in the I-FIFO the destination bus master drains the data from the I-FIFO. The IWM field in DMA_CS ...
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Figure 9: Linked List DMA Operation Register information copied to DMA Control and Address Registers The maximum data transfer size for a Linked List DMA is 1 Mbyte because only CNT[19:2] bits are loaded from the command packet. QSpan II ...
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Chapter 6: The DMA Channel 6.4.1 Initiating a Linked List Mode DMA Operation To initiate a Linked List Mode DMA, the command packets described in the previous section must be set up in QBus memory or PCI bus memory. The ...
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IDMA/DMA_CNT[19:2] • DMA_CPP[31:4] The DMA Channel then starts the DMA transfer described by the command packet. The command packet pointer register (DMA_CPP) points to the next command packet, and not to the command packet that is being executed. At ...
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Chapter 6: The DMA Channel 6.4.2 Terminating a Linked List Mode DMA Operation To terminate a Linked List DMA operation, set the IRST_REQ bit this case, the Linked List DMA is terminated and the IRST status bit ...
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Chapter 7: The Register Channel This chapter describes the QSpan II’s Register Channel. The following topics are discussed: • “Register Access Fairness” on page 110 • “Register Access from the PCI Bus” on page 111 • “Register Access from the ...
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Chapter 7: The Register Channel Figure 10: Register Channel — Functional Diagram PCI Interface PCI Master Module PCI Bus PCI Target Module 7.2 Register Access Fairness QSpan II can be configured to make register access fairer by setting the Register ...
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Register Access from the PCI Bus The QCSRs can be accessed through Configuration cycles or in Memory space (see the following figure). These accesses are discussed in the following sections. Default ownership of the Register Channel is granted to ...
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Chapter 7: The Register Channel QSpan II registers can be accessed in Memory space but not in I/O space. To access QCSRs from PCI bus Memory space necessary to set the Memory Space bit in the PCI_CS register ...
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Register Access from the QBus QSpan II’s registers can be selected by an external master from the QBus with the CSREG_ chip-select pin. Since the QSpan II registers span 4K, only the lower 12 bits of the QBus address ...
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Chapter 7: The Register Channel 7.4.1 Examples of QBus Register Accesses The following table illustrates Big-Endian access to bits 15-08 of the PCI_CLASS register. This table shows the address and size signals required to access this byte. This table also ...
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Address Phase of PCI Configuration Cycles The type of Configuration cycle that is generated on the PCI bus — Type 0 or Type 1 — is determined by the TYPE bit of the CON_ADD register (see Table 115 on ...
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Chapter 7: The Register Channel Table 40: PCI AD[31:16] lines asserted as a function of DEV_NUM field DEV_NUM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.4.3.1 Data Phase of PCI Configuration ...
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Register Access Synchronization QSpan II supports non-simultaneous access to its registers from the QBus Interface and the PCI Interface. This feature presents a synchronization issue. QSpan II does not have the ability to lock out register accesses from one ...
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Chapter 7: The Register Channel 7.6 Mailbox Registers QSpan II has four 32-bit mailbox registers which provide an additional communication path between the PCI bus and the QBus. The mailboxes support read and write accesses from either bus and can ...
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Chapter 8: The Interrupt Channel This chapter describes the function of the QSpan II Interrupt Channel. The following topics are discussed: • “Hardware-Triggered Interrupts” on page 120 • “Software-Triggered Interrupts” on page 121 • “Interrupt Acknowledge Cycle” on page 125 ...
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Chapter 8: The Interrupt Channel 8.2 Hardware-Triggered Interrupts In order for an input to trigger an interrupt on the opposite interface, the corresponding enable bit must be set in the INT_CTL register (see Table 120 on page 269). For example, ...
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Table 41: Mapping of Hardware-Initiated Interrupts (INT_CTL, see Input Table 120 on page 269) INT# PERR# SERR# QINT_ If INT_EN is set, then the assertion of INT# causes QINT_ to be asserted until INT# is negated and the INT_IS bit ...
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Chapter 8: The Interrupt Channel Table 42: Interrupt Source, Enabling, Mapping, Status and Clear bits Source Bits Source Write 1 to clear QBus Slave Channel Errors (Error on the PCI bus) PCI Bus Error ES in PB_ERRCS (see Table 97 ...
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Table 42: Interrupt Source, Enabling, Mapping, Status and Clear bits (Continued) Source Bits Source Write 1 to clear Power State PME_EN PCI_PMCS Changed (see Table 85 on Interrupt Status page 224) Outbound - Post_List Not Empty Status Inbound - Post_List ...
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Chapter 8: The Interrupt Channel Four software interrupt bits are provided: Software Interrupt 0 through 3. Setting a software interrupt bit (SI3, SI2, SI1, or SI0) triggers the interrupt status (see the following table) and causes the QSpan II to ...
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The MD_PED bit already generates an interrupt, so this functionality will not cause the PCSR_EN status bit to be set. To clear the interrupt and interrupt status bit, write PCSR_IS in the INT_STAT (see Table 119 on ...
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Chapter 8: The Interrupt Channel 126 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Chapter 9: The EEPROM Channel This chapter describes the QSpan II’s EEPROM Channel. The following topics are discussed: • “EEPROM Configuration and Plug and Play Compatibility” on page 129 2 • “EEPROM I • “Mapping of EEPROM Bits to QSpan ...
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Chapter 9: The EEPROM Channel Figure 15: EEPROM Channel — Functional Diagram PCI Interface PCI Master Module PCI Bus PCI Target Module QSpan II supports an additional scheme to be Plug and Play compatible without the use of an EEPROM. ...
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EEPROM Configuration and Plug and Play Compatibility There are two ways to configure the EEPROM to allow the QSpan II to boot as a PCI Plug and Play compatible device: • The EEPROM can be configured before it is ...
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Chapter 9: The EEPROM Channel While the registers are being loaded from the EEPROM, all accesses to the QSpan external PCI bus master are terminated with a retry. During this period, write accesses to the EEPROM programmable ...
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PCI Configuration Base Address for Target 0 (PCI_BST0 register): see Table 75 on page 214 • PCI Configuration Base Address for Target 0 (PCI_BST1 register): see Table 77 on page 216 Table 44: Destination of EEPROM Bits Read Bit ...
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Chapter 9: The EEPROM Channel Table 44: Destination of EEPROM Bits Read Bit 7 Bit 6 Byte [23] [22] 10 (TA) (TA) QBSI0_AT [7] [6] 11 (BS) (BS) [15] [14] 12 (DID) (DID) [7] [6] 13 (DID) (DID) [15] [14] ...
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Table 44: Destination of EEPROM Bits Read Bit 7 Bit 6 Byte [7] [6] 20 (MIN_GNT) (MIN_GNT) (MIN_GNT) PCI_MISC1 MISC_CTL2 [7] [ (INT_PIN0) (!PCI_DIS ) (PME_SP) PCI_BST0 PCI_BST1 22 [7] (PREF) [6] (PREF) a. The top part of ...
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Chapter 9: The EEPROM Channel Writes complete normally on the QBus and the PCI bus regardless of the state of the ACT bit. However, if the ACT bit the write does not change the content of the ...
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Reading VPD Data QSpan II implements 8 bits of address for accessing the EEPROM (maximum of 256 bytes). The VPD address must be 32-bit aligned. QSpan II will add 0x20 to the VPD address to generate an EEPROM address ...
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Chapter 9: The EEPROM Channel 136 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Chapter 10 This chapter discusses the I following topics are described: • “Inbound Messaging” on page 138 • “Outbound Messaging” on page 139 • “I O Operation” on page 140 2 • “Summary of I • “I O ...
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Chapter 10 Messaging Unit 2 Figure 17 Messaging Unit — Functional Diagram 2 PCI Interface PCI Master Module PCI Bus PCI Target Module 10.2 Inbound Messaging The Inbound Post_List FIFO (IP_FIFO) contains MFAs for message frames ...
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Figure 18 Implementation 2 IOF_TP (incremented by QSpan II) Write to Outbound Queue External PCI Host Read from Outbound Queue IOP_BP (incremented by the QSpan II) IIP_TP (incremented by the QSpan II) Write to Inbound Queue External PCI ...
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Chapter 10 Messaging Unit 2 QSpan II then supplies the data from the Bottom of the Outbound Post-List FIFO. If the Outbound Post-List FIFO is empty, the QSpan II returns 0xFFFF_FFFF to the PCI Host or IOP on ...
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The QBus Host then programs the Inbound Free_List pointers in the QSpan II registers. The location in the Inbound Free_List FIFO (for example, if the location of 2 IF_FIFO is at QIBA, then IIF_BP = 0). ...
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Chapter 10 Messaging Unit 2 10.5.1.1 Inbound I O Message 2 1. The host gets an MFA by reading from offset 0x040 from the first Base Address Register (I2O_BAR). This causes the QSpan II to generate a QBus ...
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The Host is notified of the Outbound message either through the PCI interrupt or by polling the status bit. It then initiates a PCI memory read access at offset 0x044 from the first BAR in the QSpan II’s Configuration ...
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Chapter 10 Messaging Unit 2 144 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Chapter 11: PCI Bus Arbiter This chapter explains the QSpan II’s PCI bus arbiter. The following topics are discussed: • “Arbitration Scheme” on page 146 • “Bus Parking” on page 148 11.1 Overview QSpan II has an integrated PCI bus ...
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Chapter 11: PCI Bus Arbiter Figure 19: PCI Bus Arbiter — Functional Diagram PCI Interface PCI Master Module PCI Bus Arbiter PCI Bus PCI Target Module 11.2 Arbitration Scheme To maintain arbitration fairness, the PCI bus arbiter assigns bus masters ...
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Figure 20: PCI Bus Arbiter — Arbitration Scheme Master C Arbitration Order Level 1, Level 1, Level 1, Level 0 For example, if all bus masters assert Request ...
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Chapter 11: PCI Bus Arbiter 11.3 Bus Parking Bus parking is supported on the last bus master pre-determined bus master. This depends on the setting of the PCI Bus Parking Scheme (PARK) bit and the Select Master ...
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Chapter 12: CompactPCI Hot Swap Friendly Support This chapter discusses CompactPCI Hot Swap Friendly capabilities of the QSpan II. The following topics are explained: • “Hot Swapping with the QSpan II” on page 150 • “CompactPCI Hot Swap Card Insertion” ...
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Chapter 12: CompactPCI Hot Swap Friendly Support Figure 21: CompactPCI Hot Swap — Functional Diagram PCI Interface PCI Master Module PCI Bus Arbiter PCI Bus CompactPCI Hot Swap PCI Target Module 12.2 Hot Swapping with the QSpan II The CompactPCI ...
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QSpan II also monitors the board healthy signal (HEALTHY# in the Hot Swap specification). This connects to QSpan II’s input signal, HS_HEALTHY_. QSpan II internally OR’s the HS_HEALTHY_ and PCI Reset (RST#) to generate an internal reset. When HS_HEALTHY_ is ...
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Chapter 12: CompactPCI Hot Swap Friendly Support Table 45: Insertion Sequence HS_ Event HEALTHY_ Long pins High connect Medium pins High connect Short pins High connect HS_ Low HEALTHY_ a asserted Turn off LED Low Close Ejector Low latch Drive ...
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Figure 22: Hot Swap Card Insertion Long Engage Short Med Engage Engage Early Power Back End Power BD_SEL# Pulled up HEALTHY# PCI RST# pre-charge (from 1) PCI Clock pre-charge PCI Signals pre-charge Engaged, tracking bus Ejector State pre-charge ENUM# LED ...
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Chapter 12: CompactPCI Hot Swap Friendly Support As the board is removed from the system, the short pin breaks contact and the HS_HEALTHY_ pin is negated, causing the QSpan II to tri-state the outputs (except HS_LED, to keep the LED ...
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Figure 23: Hot Swap Card Extraction Ejector Unlatched Early Power Back End Power BD_SEL# HEALTHY# PCI RST# (from 1) PCI Clock PCI Signals Engaged, tracking bus Ejector State Closed Open ENUM# LED LED off INS bit Cleared/Unarmed EXT bit Cleared/Armed ...
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Chapter 12: CompactPCI Hot Swap Friendly Support 156 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Chapter 13: PCI Power Management Event Support This chapter explains PCI Power Management Support for the QSpan II. It focusses on the Power Management Support output signal (PME#). 13.1 Overview QSpan II provides a PCI Power Management interface that is ...
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Chapter 13: PCI Power Management Event Support PME# has additional electrical requirements beyond standard an open drain signal that allows shared between devices which are powered off, and those that are powered on. This isolation circuitry must ...
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Chapter 14: Reset Options This chapter discusses Reset options for the QSpan II. The following topics are examined: • “Types of Resets” on page 159 • “Configuration Options at Reset” on page 161 14.1 Types of Resets QSpan II can ...
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Chapter 14: Reset Options The QBus Software Reset Control (SW_RST) bit in the MISC_CTL register (see Table 127 on page 280) controls the QBus Reset output (RESETO_). One of the uses of this mechanism is to keep the QBus in ...
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The QCLK and PCLK inputs are necessary for software resets. That is, these clocks are required in order for the QSpan II to negate RESETO_. This is due to the fact that for a software reset, the QSpan II's registers ...
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Chapter 14: Reset Options 14.2.2 QBus Master and Slave Modes QSpan II has four Master and Slave modes that are determined by the BDIP_ and the SIZ[1] signals at reset. The QBus can be in MC68360 (QUICC), MPC860 (PowerQUICC) or ...
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Chapter 15: Hardware Implementation Issues This chapter briefly describes hardware implementation issue for the QSpan II. The following topics are discussed: • “Test Mode Pins” on page 163 • “JTAG Support” on page 164 • “Decoupling Capacitors” on page 164 ...
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... There is an internal pull-up resistor on TMS which will keep the QSpan II’s JTAG controller in a reset state without requiring TRST low. The current revision of the Boundary Scan Description Language (BSDL) file for the QSpan II (CA91L862A) is available on the Tundra website at www.tundra.com. 15.3 Decoupling Capacitors ...
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Chapter 16: Signals This chapter describes the signals which are supported by the QSpan II. The following topics are discussed: • “MC68360 Signals: QUICC” on page 167 • “MPC860 Signals: PowerQUICC” on page 171 • “M68040 Signals” on page 175 ...
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Chapter 16: Signals 16.2 Overview QSpan II’s QBus Interface defines a number of signals that can be mapped to MC68360 (QUICC), MPC860 (PowerQUICC), or M68040 buses (see the following table). Table 50: QBus Signal Names Compared to Motorola Signals QBus ...
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MC68360 Signals: QUICC A[31:0] Address Bus: address for the current bus cycle driven by the QSpan II when it is the QBus master and input when QBus slave qualified at the start of a transaction ...
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Chapter 16: Signals 16.3 MC68360 Signals: QUICC (Continued) BERR_/TEA_ Bus Error: used to indicate a bus error that occurs during a transaction. It can be used in conjunction with HALT_/TRETRY_ to indicate a busy-retry to the bus master ...
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MC68360 Signals: QUICC (Continued) DONE_ IDMA Done: indicates that the IDMA controller has completed the current sequence of IDMA operations, and that the QSpan II should no longer use DREQ_ to request transactions. Setup for DONE is to falling ...
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Chapter 16: Signals 16.3 MC68360 Signals: QUICC (Continued) QCLK QBus Clock: All devices intended to interface with QBus side of the QSpan II must be synchronized to this clock. The QCLK can operate MHz (with an MC68360 ...
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MPC860 Signals: PowerQUICC A[31:0] Address bus: address for the current bus cycle driven by the QSpan II when it is the QBus master and input as slave qualified at the start of a transaction by ...
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Chapter 16: Signals 16.4 MPC860 Signals: PowerQUICC (Continued) BR_ Bus Request: used by the QSpan II to request ownership of the QBus. BR_, along with BG_ and BB_/BGACK_, provide the three-wire handshake for QBus arbitration. BR_ is asserted and released ...
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MPC860 Signals: PowerQUICC (Continued) DSACK1_/TA_ Transaction Acknowledge: driven by the addressed slave to acknowledge the completion of a data transfer on the QBus slave the QSpan II terminates all normal bus cycles by asserting TA_. QSpan II ...
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Chapter 16: Signals 16.4 MPC860 Signals: PowerQUICC (Continued) SIZ[1:0] Size: indicates the number of bytes to be transferred during a bus cycle. The value of the Size bits, along with the lower two address bits and the port width, define ...
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The following table applies to MC68360 and MPC860 SIZ[1:0] signals. Table 51: MC68360/MPC860 Encoding for the SIZ[1:0] Signal SIZ[ 16.5 M68040 Signals A[31:0] Address bus: Address for the current bus cycle driven by the ...
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Chapter 16: Signals 16.5 M68040 Signals (Continued) BG_ Bus Grant: indicates that the QSpan II may become the next M68040 bus master. BG_, along with BR_ and BB_/BGACK_, provide the three-wire handshake for M68040 bus arbitration. BG_ is sampled on ...
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M68040 Signals (Continued) QCLK QBus Clock: All devices intended to interface with QBus side of the QSpan II must be synchronized to this clock. QCLK can operate up to 40MHz. QINT_ QBus Interrupt output, this open drain ...
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Chapter 16: Signals 16.5 M68040 Signals (Continued) TEA_ See BERR_/TEA_ TIP_ See BURST_/TIP_ TS_ Transfer Start: asserted for one clock period to indicate the start of a transfer. The following table describes the signal encoding for M68040 SIZ[1:0] signals. Byte ...
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PCI Bus Signals (Continued) EXT_REQ#[6:1] External Request: used by an external device to indicate to the QSpan II PCI bus arbiter that it wants ownership of the PCI bus. The QSpan II drives the unused EXT_REQ#[6:1] pins high when ...
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Chapter 16: Signals 16.6 PCI Bus Signals (Continued) REQ# Bus Request: used by the QSpan II to indicate that it requires the use of the PCI bus; this is an output when the QSpan II uses an external arbiter. REQ# ...
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Miscellaneous Signals ENID ENID: EEPROM Loading Reset Option. If ENID is sampled high after a PCI reset, then the QSpan II will download register information from the EEPROM. PCI_ARB_EN PCI Arbiter Enable: If PCI_ARB_EN is sampled high at the ...
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Chapter 16: Signals 16.9 JTAG Signals TMS Test Mode Select: Used to control the state of the Test Access Port controller TDI Test Input: Used (in conjunction with TCK) to shift data and instructions into the Test Access Port (TAP) ...
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Chapter 17: Signals and DC Characteristics This chapter discusses QSpan II signals and DC characteristics. The following topics are explained: • “Packaging and Voltage Level Support” on page 184 • “Signals and DC Characteristics” on page 184 • “Pinout” on ...
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Chapter 17: Signals and DC Characteristics 17.2 Packaging and Voltage Level Support QSpan II is available in two packages: • mm, 1.0 mm ball pitch, 256 PBGA • mm, 1.27 mm ball ...
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Table 54: 3.3V PCI I/O Signaling AC/DC Characteristics (V Symbols Parameters V Input low voltage IL V Input high voltage IH I Input high current IH I Input low current IL V Output low voltage OL V Output high voltage ...
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Chapter 17: Signals and DC Characteristics Table 55: 5V PCI I/O Signaling AC/DC Electrical Characteristics Symbols Parameters V Input low voltage IL V Input high voltage IH I Input high current IH I Input low current IL V Output low ...
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Table 56: Pin List for QSpan II Signals PBGA PBGA Pin Name Ball # Ball # A[31:0] See See Table 58 Table 58 AD[31:0] See See Table 57 Table 57 AS_ L16 N20 BB_/BGACK_ L2 R1 ...
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Chapter 17: Signals and DC Characteristics Table 56: Pin List for QSpan II Signals (Continued PBGA PBGA Pin Name Ball # Ball # DONE_ J15 K17 DREQ_ G13 J17 DS_ C10 A13 DSACK0_ G3 J4 DSACK1_/ ...
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Table 56: Pin List for QSpan II Signals (Continued PBGA PBGA Pin Name Ball # Ball # PCI_ARB_EN C4 B4 PCI_DIS K3 M4 PCLK P8 W11 PERR# N9 U11 PME QCLK D8 A10 QINT_ ...
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Chapter 17: Signals and DC Characteristics Table 56: Pin List for QSpan II Signals (Continued PBGA PBGA Pin Name Ball # Ball # TCK H13 J20 TDI K15 L18 TDO K13 M19 TEA_ TEST1 B12 B15 ...
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Table 57: PCI Bus Address/Data Pins 17 mm Signal PBGA AD0 N15 AD1 N14 AD2 T16 AD3 P15 AD4 T14 AD5 T13 AD6 P14 AD7 P12 AD8 T10 AD9 P11 AD10 N11 AD11 P10 AD12 R10 AD13 T9 AD14 T8 ...
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Chapter 17: Signals and DC Characteristics Table 58: QBus Address Pins 17 mm Signal PBGA A0 G14 A1 G16 A2 G15 A3 F14 A4 F16 A5 E16 A6 C13 A7 B16 A8 C14 A9 A15 A10 D12 A11 C11 A12 ...
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Table 59: QBus Data Pins 17 mm Signal PBGA D0 F15 D1 E15 D2 E14 D3 D16 D4 D15 D5 F13 D6 E13 D7 D14 D8 C16 D9 C15 D10 B14 D11 B15 D12 D10 D13 A11 D14 D9 D15 ...
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Chapter 17: Signals and DC Characteristics Table 61: Pin Assignments for Power ( PBGA a F12 A16 G12 H12 J12 E10 K5 E11 K12 E12 L5 F5 L12 ...
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Table 63: Pin Assignments for Ground ( PBGA F10 H10 F11 H11 G10 J10 G11 J11 Table 64: No-connect Pin Assignments 17 ...
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Chapter 17: Signals and DC Characteristics 17.4 Pinout Table 65: Pinout of 17x17 mm Package A1. N/C D5. D[21] A2. D[25] D6. A[23] A3. D[23] D7. A[17] A4. D[22] D8. QCLK A5. DP[0] D9. D[14] A6. A[25] D10. D[12] A7. ...
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Table 66: Pinout of 27x27 mm Package A1. VSS C13. A[14] A2. D[26] C14. A[11] A3. D[22] C15. TEST3 A4. DP[2] C16. A[10] A5. VDD C17. A[6] A6. A[24] C18. D[8] A7. A[22] C19. VDD A8. VSS C20. D[4] A9. ...
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Chapter 17: Signals and DC Characteristics 198 QSpan II PCI-to-Motorola Processor Bridge Manual 8091862.MA001.06 ...
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Appendix A: Registers This Appendix describes the QSpan II’s registers. The following topics are discussed: • “Register Map” on page 201 • “Registers” on page 206 A.1 Overview The 4 Kbytes of QSpan II Control and Status Registers (QCSRs) promotes ...
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Appendix A: Registers A.2 Terminology G_RST N/A PCI_RST 0x R R/W R/W/E R/WQ R/WP R/WQ/E The bit combinations listed as “Reserved” must not be set to 1. All bits listed as “Reserved” must read back a value of 0. 200 ...