F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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®
The clock "doubling" feature may be enabled by
connecting MA4 to ground with a pull-down
resistor of 1.5K ohms at reset.
especially useful for low-power/high-integration
applications where a single clock source is used for
the entire system.
MIXED VOLTAGE OPERATION
The 65510 provides three power planes: Internal
logic and memory power, bus power, and display
power. The internal logic and memory power plane
is represented by pins 38 and 88 (VCCM) on
F65510, the bus power plane by pin 13 (VCCB) on
F65510 and the display power plane by pin 63
(VCCD) on F65510. The 65510 provides "mixed"
voltage operation where the different power planes
may each be run at 3.3V or 5V. The following
table shows the VCC pin and the corresponding
pins covered:
VCC Pin on
Power Plane
F65510
Internal Logic
38, 88
and Memory
13
Bus
63
Display
ADVANCED POWER MANAGEMENT
Normal Operating Mode
The 65510 is a full-custom, sub-micron CMOS
integrated circuit optimized for low power
consumption during normal operation. The 65510
provides CAS-before-RAS refresh cycles for the
DRAM video memory.
The 65510 provides
T65510 PIN#
F65510 PIN#
51
53
50
52
62
64
63
65
53
55
54
56
55
57
56
58
57
59
58
60
59
61
60
62
Revision 0.7
"mixed" 3.3 V and 5.0 V operation by providing
dedicated VCC pins for the 65510's internal logic,
This feature is
bus interface, and flat panel interface.
dedicated VCC can be either 3.3 V or 5.0 V, such
that the 65510 internal logic and the memory inter-
face can operate at 3.3 V and the bus interface and
panel interface can independently operate at either
3.3 V or 5.0 V. A minimum, yet flexible, clock
architecture is used to save power -- a single, fixed-
frequency clock input provides the 65510's memory
clock, and the 65510's internal rate multiplier
function provides a programmable dot clock based
on the memory clock. The 65510's performance-
enhancement features minimize the memory clock
frequency (and thus power consumption) required
to achieve a certain performance level. The 65510's
proprietary gray scaling algorithm produces a
flicker-free display with a minimum dot clock and
panel vertical refresh rate.
consumption of the controller, video memory and
flat panel all increase linearly with dot clock
frequency and panel vertical refresh rate). In order
Pins Covered
to minimize power consumption by minimizing the
internal
66 - 96
monochrome LCD, EL, and plasma flat panels.
1-49
98-100
Panel Off
In the Panel Off mode of operation, the 65510 turns
50-65
off the flat panel, and generates panel power
sequencing. The VGA sub-system remains active,
such that the CPU can read/write video memory and
I/O registers. The 65510's dot clock can be reduced
significantly, saving power.
activated by programming Extended Register XR52
bit-3. XR52 bit-5 provides the option of either tri-
stating all the video interface signals or forcing
them into an inactive state as shown in the table
below:
SIGNAL NAME
XR52 Bit 5 = 0
FLM
Inactive - driven low Tristated (Weak Pull-up)
LP
Inactive - driven low Tristated (Weak Pull-up)
SHFCLK
Inactive - driven low Tristated (Weak Pull-up)
ACDCLK
Inactive - driven low Tristated (Weak Pull-up)
P0
Inactive - driven low Tristated (Weak Pull-up)
P1
Inactive - driven low Tristated (Weak Pull-up)
P2
Inactive - driven low Tristated (Weak Pull-up)
P3
Inactive - driven low Tristated (Weak Pull-up)
P4
Inactive - driven low Tristated (Weak Pull-up)
P5
Inactive - driven low Tristated (Weak Pull-up)
P6
Inactive - driven low Tristated (Weak Pull-up)
P7
Inactive - driven low Tristated (Weak Pull-up)
6
Introduction
(Note:
the power
logic,
the
65510
supports
Panel Off mode is
SIGNAL STATUS
XR52 Bit 5 = 1
Preliminary 65510
Each
only