F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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®
VERTICAL COMPENSATION REGISTER
(XR57)
Read/Write at I/O Address 3B7h/3D7h
Index 57h
D7 D6 D5 D4 D3 D2 D1 D0
Enable V Compensation
Enable Auto V Centering
Enable Text V Stretching
Text V Stretch Method
Enable Gr V Stretching
Gr V Stretch Method
Reserved
This register is used only when flat panel
compensation is enabled.
0
Enable Vertical Compensation (EVCP)
0 Disable vertical compensation
1 Enable vertical compensation
1
Enable Automatic Vertical Centering
(EAVC)
This bit is effective only if bit-0 is 1.
0 Enable
non-automatic
centering.
The Vertical Centering
Register is used to specify the top
border. If no centering is desired then
the Vertical Centering Register can
be programmed to 0.
1 Enable automatic vertical centering.
Vertical top and bottom borders will
be computed automatically.
2
Enable Text Mode Vertical Stretching
(ETVS)
This bit is effective only if bit-0 is 1.
0 Disable text mode vertical stretching;
graphics mode vertical stretching is
used if enabled.
1 Enable text mode vertical stretching
Revision 0.7
4-3
Text Mode Vertical Stretching (TVS1-0)
These bits are effective if bits 2 and 0 are 1.
00 Double Scanning (DS) and Line
Insertion (LI) with the following
priority: DS+LI, DS, LI.
01 Double Scanning (DS) and Line
Insertion (LI) with the following
priority: DS+LI, LI, DS.
10 Double Scanning (DS) and TallFont
(TF) with the following priority:
DS+TF, DS, TF.
11 Double Scanning (DS) and TallFont
(TF) with the following priority:
DS+TF, TF, DS.
5
Enable Vertical Stretching (EVS)
This bit is effective only if bit-0 is 1.
0 Disable vertical stretching
1 Enable vertical stretching
6
Vertical Stretching (VS)
Vertical Stretching can be enabled in both
text and graphics modes.
effective only if bits 5 and 0 are 1.
0 Double Scanning (DS) and Line
vertical
Replication (LR) with the following
priority: DS+LR, DS, LR.
1 Double Scanning (DS) and Line
Replication (LR) with the following
priority: DS+LR, LR, DS.
7
Reserved (0)
97
Extension Registers
This bit is
Preliminary 65510