F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
Page 101
102
Page 102
103
Page 103
104
Page 104
105
Page 105
106
Page 106
107
Page 107
108
Page 108
109
Page 109
110
Page 110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
Page 104/154

Download datasheet (2Mb)Embed
PrevNext
®
ACDCLK CONTROL REGISTER (XR5E)
Read/Write at I/O Address 3B7h/3D7h
Index 5Eh
D7 D6 D5 D4 D3 D2 D1 D0
ACDCLK Count
ACDCLK Control
This register is used to control the duty cycle of the
ACDCLK (M) signal to the panel.
6-0
ACDCLK Count (ACDCNT)
These bits define the number of Hsyncs
between adjacent phase changes on the
ACDCLK output. These bits are effective
only when bit 7 = 0 and contents of this
register are grater than 2.
Programmed Value = Actual Value – 2
7
ACDCLK Control
0 The
ACDCLK
depending on bits 0-6 of this register
1 The ACDCLK phase changes every
frame.
Revision 0.7
BLINK RATE CONTROL REGISTER (XR60)
Read/Write at I/O Address 3B7h/3D7h
Index 60h
D7 D6 D5 D4 D3 D2 D1 D0
This register is used in all modes.
5-0
phase
changes
7-6
100
Extension Registers
Cursor Blink Rate
Char Blink Duty Cycle
Cursor Blink Rate
These bits specify the cursor blink period in
terms of number of Vsyncs (50% duty
cycle). In text mode, the character blink
period and duty cycle is controlled by bits
7-6 of this register. These bits default to
000011 (decimal 3) on reset which
corresponds to eight Vsyncs per cursor
blink period per the following formula (four
Vsyncs on and four Vsyncs off):
Programmed Value = (Actual Value) / 2 – 1
Note: In graphics mode, the pixel blink
period is fixed at 32 Vsyncs per
cursor blink period with 50% duty
cycle (16 on and 16 off).
Character Blink Duty Cycle
These bits specify the character blink (also
called 'attribute blink') duty cycle in text
mode.
Character Blink
7 6
Duty Cycle
0 0
50%
0 1
25%
1 0
50%
(default on Reset)
1 1
75%
For setting 00, the character blink period is
equal to the cursor blink period. For all
other settings, the character blink period is
twice the cursor blink period (character
blink is twice as slow as cursor blink).
Preliminary 65510