F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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From System Power Control
100 ohm
RESET
B42
RFSH/
100
n/c
A45
pF
BHE/
A54
MIO/
A34
ADL/
A20
SETUP/
A01
CMD/
B34
S0/
A32
S1/
A33
RDY
A36
DS16/
A55
CSFB/
B36
IRQ9/
n/c
B22
14.31818 MHz
n/c
B04
A23
B06
A22
B07
A21
B08
A20
B10
A19
B11
MADE24
+5V
A02
A18
B12
A17
B14
A16
B15
A15
B16
A14
B18
A13
B19
A12
B20
A11
A04
A10
A05
A9
A06
A8
A08
A7
A09
A6
A10
A5
A12
A4
A13
A3
A14
A2
A16
A1
A17
A0
A18
D15
B53
D14
B52
D13
A51
D12
B51
D11
A50
D10
A49
D09
B49
D08
B48
D07
A42
D06
A41
D05
A40
D04
B40
D03
B39
D02
A38
D01
B38
D00
A37
Circuit Example - 65510 Interface to Micro Channel Bus
Revision 0.7
100
25-50 MHz Reference Clock
CLKIN
98
STNDBY/
99
RESET
45
+5V
RFSH/
44
BHE/
46
AEN
49
ACTIND [ADL/]
2
IOWR/
1
IORD/
48
MEMW/
47
MEMR/
3
RDY
51
IRQ
(ENAVEE)
ACT02
HCT11
HCT11
43
A19
42
A18
41
A17
40
A16
39
A15
37
A14
36
A13
35
A12
34
A11
33
A10
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
A3
25
A2
24
A1
23
A0
50
VGARD
5
D15
6
D14
7
D13
8
D12
9
D11
10
D10
11
D9
12
D8
14
D7
15
D6
16
D5
17
D4
18
D3
19
D2
20
D1
21
D0
113
Application Schematic Examples
[DISA/]
{DISA/}
<DISA/>
[BHE/]
{BHE/}
<BHE/>
[MIO/]
{PMIO/}
<MIO/>
{PSTART/}
<ADS/>
[SETUP/]
{Reserved}
<LDEV/>
[CMD/]
{PCMD/}
<LCLK>
[S0/]
{Reserved}
<BS16/>
[S1/]
{PRD/}
<RD/>
[RDY]
{PRDY/}
<LRDY/>
[DS16/]
{IRQ}
<IRQ/>
Note: the ENAVEE functionality is not
available in the Micro Chanel Interface
configuration
F65510
Note: the 'T' package pinouts are
different from the 'F' package pinouts!
[A19]
(VGAHI)
{VGACS/}
[A18]
[A17]
[A16]
[A15]
[A14]
[A13]
[A12]
[A11]
[A10]
[A9]
[A8]
[A7]
[A6]
[A5]
[A4]
[A3]
[A2]
[A1]
[A0]
{A0}
<BLE/>
[CSFB/]
(ENAVDD)
Note:
To select the MC-bus pinout
configuration, the MA1 (MC/)
pin must be connected to ground
via a 1.5K resistor.
Note:
Additional data bus drive may
be
enabled
programming XR6C bit-3 = 1.
Preliminary
if
required
by
65510