F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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14.31818 MHz
n/c
B30
ISA Bus Pins
100 ohm
RESET
B02
RFSH/
n/c
B19
BHE/
C01
AEN
n/c
A11
ALE
n/c
B28
BUSCLK
n/c
B20
PI-Bus-Specific Pins
IOWR/
n/c
B13
IORD/
n/c
B14
MEMW/
n/c
B11
MEMR/
n/c
B12
RDY
n/c
A10
IRQ9
B04
NMI/
n/c
A01
0WS/
n/c
B08
IOCS16/
n/c
D02
MEMCS16/
n/c
D01
LA23
n/c
C02
LA22
n/c
C03
LA21
n/c
C04
LA20
n/c
C05
LA19
n/c
C06
LA18
n/c
C07
LA17
n/c
C08
A19
n/c
A12
A18
A13
A17
A14
A16
A15
A15
A16
A14
A17
A13
A18
A12
A19
A11
A20
A10
A21
A9
A22
A8
A23
A7
A24
A6
A25
A5
A26
A4
A27
A3
A28
A2
A29
A1
A30
A0
A31
+5V = B3, B29, D16
D15
C18
D14
C17
D13
C16
D12
C15
D11
C14
D10
C13
D09
C12
D08
C11
GND = B1, B10,B31,D18
D07
A02
D06
A03
D05
A04
D04
A05
D03
A06
D02
A07
D01
A08
D00
A09
Circuit Example - 65510 Interface to PI Bus (x86 SL)
Revision 0.7
100
25-50 MHz Reference Clock
98
From System Power Control
99
100
45
Pullup
pF
44
PMIO#
46
CPU-X02
PSTART#
49
CPU-R02
2
Pullup
PCMD#
1
CPU-U02
48
Pullup
PW/R#
47
CPU-T02
PRDY#
3
CPU-V03
51
386 SL CPU
(LGA Package)
VGACS#
CPU-V02
43
42
41
40
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
50
n/c
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
21
114
Application Schematic Examples
CLKIN
STNDBY/
RESET
RFSH/
[DISA/]
{DISA/}
<DISA/>
BHE/
[BHE/]
{BHE/}
<BHE/>
AEN
[MIO/]
{PMIO/}
<MIO/>
ACTIND [ADL/]
{PSTART/}
<ADS/>
IOWR/
[SETUP/]
{Reserved}
<LDEV/>
IORD/
[CMD/]
{PCMD/}
<LCLK>
MEMW/
[S0/]
{Reserved}
<BS16/>
MEMR/
[S1/]
{PRD/}
<RD/>
RDY
[RDY]
{PRDY/}
<LRDY/>
IRQ
[DS16/]
{IRQ}
<IRQ/>
(ENAVEE)
Note: If IRQ is used, ENAVEE
functionality is lost!
F65510
Note: the 'T' package pinouts are
different from the 'F' package pinouts!
A19
[A19]
(VGAHI)
{VGACS/}
A18
[A18]
A17
[A17]
A16
[A16]
A15
[A15]
A14
[A14]
A13
[A13]
A12
[A12]
A11
[A11]
A10
[A10]
A9
[A9]
A8
[A8]
A7
[A7]
A6
[A6]
A5
[A5]
A4
[A4]
A3
[A3]
A2
[A2]
A1
[A1]
A0
[A0]
{A0}
<BLE/>
VGARD
[CSFB/]
(ENAVDD)
D15
D14
D13
Note:
To select the PI-bus pinout
D12
configuration, the MA0 (LB/)
D11
D10
and MA1 (MC/) pins must
D9
both be connected to ground
D8
via a 1.5K resistor.
Note:
Additional data bus drive
D7
may
be
D6
programming XR6C bit-3 = 1.
D5
D4
D3
D2
D1
D0
Preliminary
enabled
by
65510