F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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D/C#
CPU-A11
CPU-24
BHE#
CPU-19
M/IO#
CPU-A12
CPU-23
ADS#
CPU-E14
CPU-16
NA#
CPU-D13
CPU-6
CLK2
CPU-F12
CPU-15
BS16#
CPU-C14
W/R#
CPU-B10
CPU-25
RDY#
CPU-G13
CPU-7
INTR
CPU-B7
CPU-40
NMI
CPU-B8
CPU-38
BUSY#
CPU-B9
CPU-34
ERROR#
CPU-A8
CPU-36
PEREQ
CPU-C8
CPU-37
LOCK#
CPU-C10
CPU-24
HOLD
CPU-D14
CPU-4
HLDA
CPU-M14
CPU-3
A23
CPU-L1
CPU-80
A22
CPU-K2
CPU-79
A21
CPU-K1
CPU-76
A20
CPU-J1
CPU-75
386DX CPU
386SX CPU
HCT08
386DX CPU
BE3#
CPU-A13
BE1#
CPU-C13
BE0#
CPU-E12
BE2#
CPU-B13
386DX CPU
386SX CPU
D15
CPU-M11
CPU-81
D14
CPU-P12
CPU-82
D13
CPU-P13
CPU-83
D12
CPU-N12
CPU-86
D11
CPU-N13
CPU-87
D10
CPU-M12
CPU-88
D09
CPU-N14
CPU-89
D08
CPU-L13
CPU-90
386DX CPU
386SX CPU
D07
CPU-K12
CPU-92
D06
CPU-L14
CPU-93
D05
CPU-K13
CPU-94
D04
CPU-K14
CPU-95
D03
CPU-J14
CPU-96
D02
CPU-H14
CPU-99
D01
CPU-H13
CPU-100
D00
CPU-H12
CPU-1
Circuit Example - 65510 Interface to 386 SX/DX Local Bus
Revision 0.7
25-50 MHz Reference Clock
From System Power Control
SYSRESET
n/c
Pullup
LDEV#
n/c
LB Ctrl Logic
(2X CPU Clock)
IRQ9
System Intrpt Controller
n/c
n/c
n/c
n/c
n/c
n/c
74HCT260
74HCT08
A19
CPU-H3
CPU-74
A18
CPU-H2
CPU-73
A17
CPU-H1
CPU-72
A16
CPU-G1
CPU-70
A15
CPU-F1
CPU-66
A14
CPU-E1
CPU-65
A13
CPU-E2
CPU-64
A12
CPU-E3
CPU-62
A11
CPU-D1
CPU-61
A10
CPU-D2
CPU-60
A9
CPU-D3
CPU-59
A8
CPU-C1
CPU-58
A7
CPU-C2
CPU-56
A6
CPU-C3
CPU-55
A5
CPU-B2
CPU-54
A4
CPU-B3
CPU-53
A3
CPU-A3
CPU-52
A2
CPU-C4
CPU-51
A1
CPU-18
BLE#
CPU-17
386DX CPU
386SX CPU
n/c
115
Application Schematic Examples
100
CLKIN
98
STNDBY/
99
RESET
45
RFSH/
[DISA/]
{DISA/}
<DISA/>
44
BHE/
[BHE/]
{BHE/}
<BHE/>
46
AEN
[MIO/]
{PMIO/}
<MIO/>
49
ACTIND [ADL/]
{PSTART/}
<ADS/>
2
IOWR/
[SETUP/]
{Reserved}
<LDEV/>
1
IORD/
[CMD/]
{PCMD/}
<LCLK>
48
MEMW/
[S0/]
{Reserved}
<BS16/>
47
MEMR/
[S1/]
{PRD/}
<RD/>
3
RDY
[RDY]
{PRDY/}
<LRDY/>
51
IRQ
[DS16/]
{IRQ}
<IRQ/>
(ENAVEE)
Note: If IRQ is used, ENAVEE
functionality is lost!
F65510
Note: the 'T' package pinouts are
different from the 'F' package pinouts!
43
A19
[A19]
(VGAHI)
{VGACS/}
42
A18
[A18]
41
A17
[A17]
40
A16
[A16]
39
A15
[A15]
37
A14
[A14]
36
A13
[A13]
35
A12
[A12]
34
A11
[A11]
33
A10
[A10]
32
A9
[A9]
31
A8
[A8]
30
A7
[A7]
29
A6
[A6]
28
A5
[A5]
27
A4
[A4]
26
A3
[A3]
25
A2
[A2]
24
A1
[A1]
23
A0
[A0]
{A0}
<BLE/>
50
VGARD
[CSFB/]
(ENAVDD)
5
D15
6
D14
7
D13
8
D12
9
D11
10
D10
11
D9
12
Note: To select the local bus pinout
D8
configuration, the MA0 (LB/)
pin must be connected to
14
D7
ground via a 1.5K resistor.
15
D6
16
D5
17
D4
18
D3
19
D2
20
D1
21
D0
Preliminary
65510