F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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FOR REFERENCE ONLY: BUS TIMING CHARACTERISTICS
Symbol Parameter
T
Address Latch Pulse Width
ADL
T
Delay from Start of Cycle to Command Strobe
CD
T
Delay from Address Valid to Command Strobe
CDM
T
Command Strobe Pulse Width (Asynchronous Cycle)
CMD
T
Command Strobe Pulse Width (Synchronous Cycle)
CMD
T
Delay from End of Command to Start of Next Cycle
END
T
Address Setup to Start of Cycle
AS
T
Address Setup to Start of Command
ASL
T
Address Hold from Start of Command
AH
T
Read Data Delay from Start of Command
RDD
T
Read Data Setup to End of Command
RDS
T
Read Data Hold from End of Command (Data Turnoff)
RDH
T
Write Data Delay from Start of Command
WDD
T
Write Data Hold from End of Command (Data Turnoff)
WDH
T
Delay from Address to IOCS16/
ICS
T
Delay from Address to MEMCS16/, DS16/, CSFB/
MCS
T
Delay from Start of Command to Start of 0WS/ (16-bit)
ZWS
T
Delay from Start of Command to Start of 0WS/ (8-bit)
ZWS
T
Delay to End of 0WS/ from End of Command
ZWH
T
Delay to Start of RDY from Start of Command
RDY
T
Delay to Start of RDY from Address & Status Valid
RDYM
T
Delay from End of RDY to End of Command
RDYH
T
Delay from Start of Cycle to RDY/ Low (Sync)
RDB
T
Delay from Start of Cycle to RDY/ Low (Async)
RDB
T
Delay from End of Command to RDY/ High
RDBH
Note: PC bus specifications correspond to an 8 MHz bus (SYSCLK period of 125nS) (12 MHz bus SYSCLK period would be
80nS)
MC bus specifications correspond to a 25MHz CPU (PS/2 Model 80)
PI bus specifications correspond to 20 MHz CPU; timing specifications scale with clock frequency for other CPU speeds
0WS/ is synchronous to SYSCLK in some systems and has other timing restrictions than shown above (esp. for 8-bit
cycles)
Either 0WS/ or RDY may be asserted, but not both (PC Bus)
0WS/ is used for memory accesses only; it works for I/O writes in some systems but not for I/O reads
At the end of the cycle, RDY and 0WS/ should be driven high before being tri-stated
RDY in the MC bus should be generated based on address, status, and MIO/ only
Revision 0.7
8 MHz
12.5 MHz 20 MHz
PC Bus
MC Bus
50 min
40 min
50 min
40 min
109 min
85 min
176 min
90 min
176 min
90 min
50 min
40 min
0 min
10 min
29 min
5 min
5 min
187 max
60 max
62 min
30 min
0 min
0 min
30 max
30 max
40 max
0 max
10 min
10 min
40 max
40 max
90 max
66 max
55 max
40 max
1 min
30 max
30 max
30 max
1 SYSCLK
60 min
140
Electrical Specifications
PI Bus
Units
50 min
nS
50 min
nS
nS
70 min
nS
40 min
nS
0 min
nS
10 min
nS
nS
–5 min
nS
nS
29 min
nS
12 min
nS
30 max
nS
14 max
nS
10 min
nS
40 max
nS
nS
nS
nS
SYSCLK
nS
nS
nS
nS
28 max
nS
92 min
nS
20 max
nS
Preliminary
65510