F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 145/154:

Unlatched (LA) Addresses

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Unlatched (LA) Addresses

& Status†
Latched (SA) Addresses
(& BHE/ on the PC)
IOCS16/ (PC)
CSFB/ (MC), DS16/ (MC)
MEMCS16/ (PC)
ALE (PC only, non-DMA cycles)
(high for DMA & master cycles)
ADL/ (MC), PSTART/ (PI)
CMD/, IORD/, IOWR/,
MEMR/, MEMW/
0WS/ (PC Mem Only)
RDY (PC, MC)
RDY/ (PI)
Data (Read)
Data (Write)
† Status signals are: MIO/ (MC, PI), S0/ & S1/ (MC), AEN (PC-I/O), BHE/ (MC, PI), RD/ (PI), RFSH/ (PC-Mem)
Note: Addresses must be latched on the leading edge of PSTART/ for the PI bus (addresses are not valid on the trailing
edge)
Addresses should be latched on the trailing edge of ALE for the PC bus (addresses are not valid on the leading edge)
Addresses should be latched on the leading or trailing edge of ADL/ for the MC bus (addresses are valid on both edges)
Addresses may be latched on the leading edge of CMD/ instead on PC and MC bus (not PI!) if ALE or ADL/ are not
used
PC / MC / PI Bus Timing Characteristics for Non-Bus-Master Peripheral Devices
Revision 0.7
Start of
Cycle
T
ICS
T
MCS
T
AH
T
ASL
T
ADL
T
AS
T
CDM
T
T
T
CD
CMD
END
T
ZWS
T
RDYM
T
T
RDY
RDYH
T
RDB
T
RDD
T
RDS
T
WDD
141
Electrical Specifications
End of
Cycle
T
ZWH
T
RDBH
T
RDH
T
WDH
Preliminary
65510