F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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CHIP ARCHITECTURE
The 65510 integrates five major internal modules:
Sequencer
The Sequencer generates all CPU and display
memory timing. It controls CPU access of display
memory by inserting cycles dedicated to CPU
access. It also contains mask registers which can
prevent writes to individual display memory planes.
CRT Controller
The CRT Controller generates all the sync and
timing signals for the display and also generates the
multiplexed row and column addresses used for
both display refresh and CPU access of display
memory.
Graphics Controller
The Graphics Controller interfaces the 8 or 16-bit
CPU data bus to the 32-bit internal data bus used by
the four planes (Maps) of display memory. It also
latches and supplies display memory data to the
Attribute Controller for use in refreshing the screen
image. For text modes this data is supplied in
parallel form (character generator data and attribute
code); for graphics modes it is converted to serial
form (one bit from each of four bytes form a single
pixel). The Graphics Controller can also perform
any one of several types of logical operations on
data while reading it from or writing it to display
memory or the CPU data bus.
Attribute Controller
The Attribute Controller generates the 4-bit-wide
video data stream used to refresh the display. This
is created in text modes from a font pattern and an
attribute code which pass through a parallel to serial
conversion. In graphics modes, the display memory
contains the 4-bit pixel data. In text and 16 color
graphic modes the 4-bit pixel data acts as an index
into a set of 16 internal color look-up registers
which generate a 6-bit color value. Two additional
bits of color data are added to provide an 8-bit
address to the VGA color palette. In 256-color
modes, two 4-bit values may be passed through the
color look-up registers and assembled into one 8-bit
video data value.
In high-resolution 256-color
modes, an 8-bit video data value may be provided
directly, bypassing the attribute controller color
lookup registers. Text and cursor blink, underline
and horizontal scrolling are also the responsibility
of the Attribute Controller.
Revision 0.7
VGA Color Palette
For compatibility, the 65510 contains an internal
256x18 color palette compatible with industry-stan-
dard Inmos/Brooktree RAMDACs. All registers in
the 03C6-03C9 I/O address range are included on-
chip, including the pixel mask register and palette
index registers. Since the 65510 does not include
CRT support, the DACs normally associated with
the RAMDAC are not included in this subsystem.
CONFIGURATION SWITCHES
The 65510 can read up to eight configuration bits.
These signals are sampled on memory address bus
bits MA0–MA7 on the falling edge of RESET. The
65510 has pull-ups on MA0-MA7 which are
enabled during the RESET active period.
status of the configuration bits (MA0-MA7) is read
into extension register XR01. The configuration bit
may be forced to a zero by using a pull-down resis-
tor value of 1.5K ohms on the appropriate configu-
ration pin (MA0-MA7). The state of MA0 and
MA1 on RESET determine EISA/ISA bus (default),
MC bus, PI bus, or 386 SX CPU interface. The
65510 provides 4mA drive (default) on the data
lines (D0-D15) to the bus which may be
programmed to 8mA drive by enabling high drive
option with extension register 6C. If higher drive is
desired, transceivers may be used in the D0-D15
path and the 65510 provides VGARD signal to
control the direction of the transceiver. VGARD
may be generated instead of ENAVDD (pin 50 on
F65510) by pulling MA3 low. The state of MA4
determines whether clock doubling is enabled.
MA2 and MA5-7 are reserved for future use. All
eight bits are latched into an extension register on
RESET so software may determine the hardware
configuration.
Also, the reserved bits may
optionally be used to read external switches or
status bits. Refer to the description of XR01 for
details on the configuration options.
LIGHT PEN REGISTERS
In the CGA and Hercules modes, the contents of the
Display Address counter are saved at the end of the
frame before being reset. The saved value can be
read in the CRT Controller Register space at indices
10h and 11h. This allows simulation of a light pen
hit in CGA and Hercules modes.
BIOS ROM INTERFACE
In typical ISA bus applications, the 65510 is placed
on the motherboard and the video BIOS is
12
Introduction
The
Preliminary 65510