F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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PIN DESCRIPTIONS
T
F
Pin # Pin # Pin Name
19
21
D0
18
20
D1
17
19
D2
16
18
D3
15
17
D4
14
16
D5
13
15
D6
12
14
D7
10
12
D8
9
11
D9
8
10
D10
7
9
D11
6
8
D12
5
7
D13
4
6
D14
3
5
D15
21
23
A0
<BLE/>
22
24
A1
23
25
A2
24
26
A3
25
27
A4
26
28
A5
27
29
A6
28
30
A7
29
31
A8
30
32
A9
31
33
A10
32
34
A11
33
35
A12
34
36
A13
35
37
A14
37
39
A15
38
40
A16
39
41
A17
40
42
A18
41
43
A19
(VGAHI)
{VGACS/}
97
99
RESET
Note: Pin names in parentheses (...) indicate alternate functions
Pin names in brackets [...] indicate MC bus functionality if different from EISA/ISA (PC/AT) bus
Pin names in braces {...} indicate PI bus functionality if different from EISA/ISA (PC/AT) bus
Pin names in brackets <...> indicate 386 SX/DX Local bus functionality if different from EISA/ISA bus
Revision 0.7
Type
Active
Description
System Data Bus
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
System Address Bus
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
In
High
When the Linear Addressing Register has a non-zero
In
High
value, this input serves as an active high Chip Select for
In
Low
ISA/EISA bus operation (or active low Chip Select for
PI bus) to access memory beyond the 1M address
range (A0-18 are used to uniquely address each of the
512K bytes in display memory).
Reset. Connect directly to ISA bus reset. Configura-
In
High
tion inputs are sampled on the falling edge. Must be
synchronous to LCLK in local bus interface mode.
Typically, ISA bus reset is synchronized to the CPU
clock by the core logic chipset.
19
Pin Descriptions
System Bus Interface
Preliminary 65510