F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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PIN DESCRIPTIONS
T
F
Pin # Pin # Pin Name
76
78
MA0
(CFG0) (LB/)
75
77
MA1
(CFG1) (MC/) Out
74
76
MA2
(CFG2)
73
75
MA3
(CFG3) (XCV/) Out
72
74
MA4
(CFG4) (CD/)
71
73
MA5
(CFG5)
70
72
MA6
(CFG6)
69
71
MA7
(CFG7)
68
70
MA8
64
66
RAS/
65
67
CASL/ (WEL/)
66
68
CASH/ (CAS/)
67
69
WE/
(WEH/)
94
96
MD0
(TSENA0/)
93
95
MD1
(ICTENA0/)
92
94
MD2
91
93
MD3
90
92
MD4
89
91
MD5
88
90
MD6
87
89
MD7
85
87
MD8
(TSENA1/)
84
86
MD9
(ICTENA1/)
83
85
MD10
82
84
MD11
81
83
MD12
80
82
MD13
79
81
MD14
78
80
MD15
If ICTENA0/ and ICTENA1/ are low with RESET high, a rising edge on CLKIN will put the chip into ' I n Circuit
Test' mode. In ICT mode, all digital signal pins become inputs which are part of a long path starting at P0 (pin 55)
and proceeding to higher pin numbers around the chip to pin 100 then to pin 1 and ending at FLM (pin 53). If all
pins in the path are high, the FLM output will be high. If any pin is low, the FLM output will be low. Thus the
chip can be checked in circuit to determine if all pins are connected properly by toggling all pins one at a time
(CLKIN last) and observing the effect on FLM. CLKIN must be toggled last because rising edges on CLKIN
with ICTENA0/ or 1/ high or RESET low will exit ICT mode. As a side effect, ICT mode effectively 3-states all
pins except FLM.
If TSENA0/ and TSENA1/ are low with RESET high , a rising edge on CLKIN will 3-state all pins. A CLKIN
rising edge without the enabling conditions exits 3-state.
Note: Pin names in parentheses (...) indicate alternate functions
Pin names in brackets [...] indicate MC bus functionality if different from EISA/ISA (PC/AT) bus
Pin names in braces {...} indicate PI bus functionality if different from EISA/ISA (PC/AT) bus
Pin names in brackets <...> indicate 386 SX/DX Local bus functionality if different from EISA/ISA bus
Revision 0.7
Type
Active
Description
Out
High
DRAM address bus
High
MC/ LB/ System Bus Configuration
Out
High
1
1
High
1
0
Out
High
0
1
Out
High
0
0
Out
High
Out
High
XCV/ = 0: ENAVDD becomes VGARD
Out
High
CD/=0: Enable Clock Doubling
Out
Low
Row address strobe
Out
Low
Column address strobe for lower byte
Out
Low
Column address strobe for upper byte
Out
Low
Write enable
I/O
High
DRAM data bus
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
I/O
High
21
Pin Descriptions
Display Memory Interface
ISA Bus
Local Bus
Micro Channel
PI Bus
Preliminary 65510