F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 
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Page 33/154:

Chips' VGA Product Family

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EXTENSION REGISTER SUMMARY: 30-5F
Reg
Register Name
XR30 (Graphics Cursor Start Address High)
XR31 (Graphics Cursor Start Address Low)
XR32 (Graphics Cursor End Address)
XR33 (Graphics Cursor X Position High)
XR34 (Graphics Cursor X Position Low)
XR35 (Graphics Cursor Y Position High)
XR36 (Graphics Cursor Y Position Low)
XR37 (Graphics Cursor Mode)
XR38 (Graphics Cursor Mask)
XR39 (Graphics Cursor Color 0)
XR3A (Graphics Cursor Color 1)
XR3B -reserved-
XR3C -reserved-
XR3D -reserved-
XR3E -reserved-
XR3F -reserved-
XR40 -reserved-
XR41 -reserved-
(Virtual EGA Switch Reg) --
XR42 -reserved-
XR43 -reserved-
XR44 Software Flag Register
XR45 -reserved-
(S/W Flag 2 / FG Color)
XR46 -reserved-
XR47 -reserved-
XR48 -reserved-
XR49 -reserved-
XR4A -reserved-
XR4B -reserved-
XR4C -reserved-
XR4D -reserved-
XR4E -reserved-
XR4F -reserved-
XR50 Panel Format
XR51 Display Type
XR52 Power Down Control (Panel Size)
XR53 Line Graphics Override
XR54 FP Interface (Alternate Misc Output)
XR55 H Compensation (Text 350_A Comp) 5
XR56 H Centering
(Text 350_B Comp)
XR57 V Compensation (Text 400 Comp)
XR58 V Centering
(Graphics 350 Comp) 8
XR59 V Line Insertion (Graphics 400 Comp) 6
XR5A V Line Replication (FP VDisp St 400) 4
XR5B Power Sequencing Delay (VD End 400) 8
XR5C -reserved-
(Weight Control Clock A) --
XR5D -reserved-
(Weight Control Clock B) --
XR5E ACDCLK Control
XR5F -reserved- (Power Down Mode Refresh) --
Reset Codes:
x = Not changed by RESET (indeterminate on power-up)
d = Set from the corresponding data bus pin on falling edge of RESET
h = Read-only Hercules Configuration Register Readback bits
Note: Check marks in the table above indicate the register listed to the left is implemented in the chip named at the top of the column
Note: 450–453 VGAs drive CRTs only, 455–457 & 655x0 VGAs drive both CRT and Flat Panel displays (Plasma, EL, and LCD)
Revision 0.7
Bits Access
Port
Reset
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
8
R/W 3B7/3D7
x x x x x x x x
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
--
--
3B7/3D7
8
R/W 3B7/3D7
x x x x x x x x
7
R/W 3B7/3D7
x x x x - 0 x x
6
R/W 3B7/3D7
0 - 0 - 0 0 0 0
3
R/W 3B7/3D7
- 0 - - x x - -
7
R/W 3B7/3D7
x x - x x x x x
R/W 3B7/3D7
- x x - - x x x
8
R/W 3B7/3D7
x x x x x x x x
7
R/W 3B7/3D7
- x x x x x x x
R/W 3B7/3D7
x x x x x x x x
R/W 3B7/3D7
- x x - x x x x
R/W 3B7/3D7
- - - - x x x x
R/W 3B7/3D7
0 1 1 1 0 0 0 1
--
3B7/3D7
--
3B7/3D7
8
R/W 3B7/3D7
x x x x x x x x
--
3B7/3D7
29
Register Summary

Chips' VGA Product Family

450 451 452 453 455 456 457 65520 65530
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– = Not implemented (always reads 0)
r = Chip revision # (starting from 0000)
0/1 = Reset to 0/1 by falling edge of RESET
Preliminary 65510
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