F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 35/154:

GLOBAL CONTROL (SETUP) REGISTERS

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GLOBAL CONTROL (SETUP) REGISTERS

The Setup Control Register and Video Subsystem
Enable registers are used to enable or disable the
VGA. The Setup Control register is also used to
place the VGA in normal or setup mode (the Global
Enable Register is accessible only during Setup
mode). The Setup Control register is used only in
ISA bus interfaces; the Video Subsystem Enable
register is used only in MC, PI, and Local Bus
configurations.
In MC and PI Bus interfaces,
disable and setup functions may also be performed
by the DISA/ and SETUP/ pins respectively. The
DISA/ pin and the various internal 'disable' bits 'OR'
together to provide multiple ways of disabling the
chip; all 'disable' bits must be off to enable access to
the chip. When the chip is 'disabled' in this fashion,
only bus access is disabled; other functions remain
operational (memory refresh, display refresh, etc).
Note: In setup mode in the IBM VGA, the Global
Setup Register (defined as port address 102) actually
occupies the entire I/O space . Only the lower 3 bits
are used to decode and select this register. To avoid
bus conflicts with other peripherals, reads should
only be performed at the 10xh port addresses while
in setup mode. To eliminate potential compatibility
problems in widely varying PC systems, the 65510
decodes the Global Setup register at I/O port 102h
only.
GENERAL CONTROL REGISTERS
Two Input Status Registers read the SENSE pin (or
Virtual Switch Register or internal comparator
output instead), pending CRT interrupt, display
enable / horizontal sync output, and vertical retrace /
video output. The Feature Control Register selects
the vertical sync function while the Miscellaneous
Output Register controls I/O address select, clock
selection, access to video RAM, memory page, and
horizontal and vertical sync polarity.
CGA / HERCULES REGISTERS
CGA Mode and Color Select registers are provided
on-chip for emulation of CGA modes. Hercules
Mode and Configuration registers are provided on-
chip for emulation of Hercules mode.
Revision 0.7
Registers
SEQUENCER REGISTERS
The Sequencer Index Register contains a 3-bit index
to the Sequencer Data Registers. The Reset Register
forces an asynchronous or synchronous reset of the
sequencer. The Sequencer Clocking Mode Register
controls
master
enable/disable and selects either an 8 or 9 dot
character clock.
A Plane/Map Mask Register
enables the color plane and write protect.
Character Font Select Register handles video
intensity and character generation and controls the
display memory plane through the character
generator select. The Sequencer Memory Mode
Register handles all memory, giving access by the
CPU to 4 / 16 / 32 KBytes, Odd / Even addresses
(planes) and writing of data to display memory.
CRT CONTROLLER REGISTERS
The CRT Controller Index Register contains a 6-bit
index to the CRT Controller Registers. Twenty eight
registers perform all display functions for modes:
horizontal and vertical blanking and sync, panning
and scrolling, cursor size and location, light pen, and
underline.
GRAPHICS CONTROLLER REGISTERS
The Graphics Controller Index Register contains a 4-
bit index to the Graphics Controller Registers. The
Set/Reset Register controls the format of the CPU
data to display memory. It also works with the
Enable Set/Reset Register.
display data to 8 bits of CPU data is accomplished
by the Color Compare Register. Data Rotate
Registers specify the CPU data bits to be rotated and
subjected to logical operations. The Read Map Select
Register reduces memory data for the CPU in the
four plane (16 color) graphics mode. The Graphics
Mode Register controls the write, read, and shift
register modes. The Miscellaneous Register handles
graphics/text, chaining of odd/even planes, and
display memory mapping.
include Color Don't Care and Bit Mask.
ATTRIBUTE CONTROLLER AND
COLOR PALETTE REGISTERS
The Attribute Controller Index Register contains a 5-
bit index to the Attribute Controller Registers. A 6th
31
Registers
clocking
functions,
video
The
Reducing 32 bits of
Additional registers
Preliminary 65510