F65510 Feature Control Register (fcr) - Intel Corporation

no-image

F65510

Manufacturer Part Number
F65510
Description
Controllers, Flat Panel VGA Controller
Manufacturer
Intel Corporation
Datasheet
string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!" string(70) "Class: /home/ecomp/master.elcodis.git/htdocs/inc/../Doc.php not found!"

FEATURE CONTROL REGISTER (FCR)

Write at I/O Address 3BAh/3DAh
Read at I/O Address 3CAh
Group 5 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Revision 0.7
1-0
7-4
2
3
Feature Control
These bits are used internal to the chip in
conjunction with the Configuration Register
(XR01). When enabled by XR01 bits 2-3
and Misc Output Register bits 3-2 = 10,
these bits determine the pixel clock
frequency typically as follows:
This preserves compatibility with drivers
developed for earlier generation Chips and
Technologies VGA controllers.
Reserved (0)
Vsync Control
This bit is cleared by RESET.
This capability is not typically very useful,
but is provided for IBM compatibility.
Reserved (0)
FCR1:0 = 00 = 40.000 MHz
FCR1:0 = 01 = 50.350 MHz
FCR1:0 = 10 = User defined
FCR1:0 = 11 = 44.900 MHz
0 VSync output on the VSYNC pin
1 Logical 'OR' of VSync and Display
Enable output on the VSYNC pin
®
Feature Control
Reserved
Vsync Control
Reserved
36
MISCELLANEOUS OUTPUT REGISTER (MSR)
Write at I/O Address 3C2h
Read at I/O Address 3CCh
Group 5 Protection
D7 D6 D5 D4 D3 D2 D1 D0
This register is cleared by RESET.
3-2
0
1
4
5
6
7
I/O Address Select . This bit selects 3Bxh
or 3Dxh as the I/O address for the CRT
Controller registers, the Feature Control
Register (FCR), and Input Status Register 1
(ST01).
RAM Enable
Clock Select. These bits usually select the
dot clock source for the CRT interface:
See extension register XR01 bits 2-3
(Configuration) and FCR bits 0-1 for
variations of the above clock selection
mapping. See also XR1F (Virtual Switch
Register)
potentially controlled by these bits.
Reserved (0)
Page Select . In Odd/Even Memory Map
Mode 1 (GR6), this bit selects the upper or
lower 64 KByte page in display memory for
CPU access: 0=select upper page; 1=select
lower page.
Reserved (0)
Reserved (0)
0 Select 3Bxh I/O address
1 Select 3Dxh I/O address
0 Prevent CPU access to display memory
1 Allow CPU access to display memory
MSR3:2 = 00 = Select CLK0
MSR3:2 = 01 = Select CLK1
MSR3:2 = 10 = Select CLK2
MSR3:2 = 11 = Select CLK3
for
General Control Registers
additional
I/O Address Select
RAM Enable
Clock Select
Reserved
Page Select
Reserved
Reserved
Preliminary 65510
functionality

Related parts for F65510