F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Page 41
42
Page 42
43
Page 43
44
Page 44
45
Page 45
46
Page 46
47
Page 47
48
Page 48
49
Page 49
50
Page 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
Page 48/154:

SEQUENCER MEMORY MODE REGISTER

Download datasheet (2Mb)Embed
PrevNext
®
SEQUENCER MEMORY MODE
REGISTER (SR04)
Read/Write at I/O Address 3C5h
Index 04h
Group 1 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
Extended Memory
Odd/Even Mode
Quad Four Mode
Reserved
0
Reserved (0)
1
Extended Memory
0 Restrict
CPU access to
Kbytes
1 Allow complete access to memory
This bit should normally be 1.
2
Odd/Even Mode
0 CPU accesses to Odd/Even addresses
are directed to corresponding odd/even
planes
1 All planes are accessed simultaneously
(IRGB color)
Bit-3 of this register must be 0 for this bit to
be effective. This bit affects only CPU write
accesses to display memory.
3
Quad Four Mode
0 CPU addresses are mapped to display
memory as defined by bit-2 of this
register
1 CPU addresses are mapped to display
memory modulo 4.
order CPU address bits select the dis-
play memory plane.
This bit affects both CPU reads and writes
to display memory.
7-4
Reserved (0)
Revision 0.7
SEQUENCER HORIZONTAL CHARACTER
COUNTER RESET (SR07)
Read/Write at I/O Address 3C5h
Index 07h
D7 D6 D5 D4 D3 D2 D1 D0
Writing to SR07 with any data will cause the
horizontal character counter to be held reset
(character counter output = 0) until a write to any
other sequencer register with any data value. The
4/16/32
write to any index in the range 0-6 clears the latch
that is holding the reset condition on the character
counter.
The vertical line counter is clocked by a signal
derived from horizontal display enable (which does
not occur if the horizontal counter is held reset).
Therefore, if the write to SR07 occurs during vertical
retrace, the horizontal and vertical counters will both
be set to zero. A write to any other sequencer
register may then be used to start both counters with
reasonable synchronization to an external event via
software control.
This is a standard VGA register which was not
documented by IBM.
The two low
44
Sequencer Registers
Don't Care
Preliminary 65510