F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 52/154:

HORIZONTAL SYNC START REGISTER

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HORIZONTAL SYNC START
REGISTER (CR04)
Read/Write at I/O Address 3B5h/3D5h
Index 04h
Group 0 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Horizontal Sync Start
This register is used for all VGA and EGA modes.
It is also used for 640 column CGA modes and
MDA/Hercules text mode. In all 320 column CGA
modes and Hercules graphics mode, the alternate
register is used.
7-0
Horizontal Sync Start
These bits specify the beginning of Hsync in
terms of Character clocks from the
beginning of the display scan. These bits
also determine display centering on the
screen.
Revision 0.7
CRT Controller Registers
HORIZONTAL SYNC END
REGISTER (CR05)
Read/Write at I/O Address 3B5h/3D5h
Index 05h
Group 0 Protection
D7 D6 D5 D4 D3 D2 D1 D0
This register is used for all VGA and EGA modes.
It is also used for 640 column CGA modes and
MDA/Hercules text mode. In all 320 column CGA
modes and Hercules graphics mode, the alternate
register is used.
4-0
Horizontal Sync End
Lower 5 bits of the character clock count
which specifies the end of Horizontal Sync.
If the horizontal sync width desired is N
clocks, then these bits = (N + contents of
CR04) and 1Fh.
6-5
Horizontal Sync Delay
These bits specify the number of character
clocks that the Horizontal Sync is delayed to
compensate for internal pipeline delays.
7
Horizontal Blank End Bit 5
This bit is the sixth bit of the Horizontal
Blank End Register (CR03).
48
Horizontal Sync End
Horizontal Sync Delay
H Blank End Bit 5
Preliminary 65510