F65510 Maximum Scan Line Register - Intel Corporation

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F65510

Manufacturer Part Number
F65510
Description
Controllers, Flat Panel VGA Controller
Manufacturer
Intel Corporation
Datasheet
®
PRESET ROW SCAN REGISTER (CR08)
Read/Write at I/O Address 3B5h/3D5h
Index 08h
Group 3 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Start Row Scan Count
Byte Panning Control
Reserved
4-0
Start Row Scan Count
These bits specify the starting row scan
count after each vertical retrace.
horizontal retrace increments the character
row scan line counter. The horizontal row
scan counter is cleared at maximum row
scan count during active display.
register is used for soft scrolling in text
modes.
6-5
Byte Panning Control
These bits specify the lower order bits for
the display start address. They are used for
horizontal panning in Odd/Even and Quad
modes.
7
Reserved (0)
Revision 0.7
MAXIMUM SCAN LINE REGISTER (CR09)
Read/Write at I/O Address 3B5h/3D5h
Index 09h
Group 2 Protection on bits 0-4
Group 4 Protection on bits 5-7
D7 D6 D5 D4 D3 D2 D1 D0
4-0
Scan Lines Per Row
These bits specify the number of scan lines
Every
in a row:
Programmed Value = Actual Value + 1
5
Vertical Blank Start Register Bit 9
This
6
Line Compare Register Bit 9
7
Double Scan
0 Normal Operation
1 Enable scan line doubling
The vertical parameters in the CRT
Controller (even for a split screen) are not
affected, only the CRTC row scan counter
(bits 0-4 of this register) and display
memory addressing screen refresh are
affected.
50
CRT Controller Registers
Scan Lines Per Row
V Blank Start Bit 9
Line Compare Bit 9
Double Scan
Preliminary 65510

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