F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 57/154:

LIGHTPEN HIGH REGISTER

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LIGHTPEN HIGH REGISTER (CR10)
Read only at I/O Address 3B5h/3D5h
Index 10h
Read-only Register loaded at line compare (the light
pen flip-flop is not implemented). Effective only in
MDA and Hercules modes or when CR03 bit-7 = 0.
LIGHTPEN LOW REGISTER (CR11)
Read only at I/O Address 3B5h/3D5h
Index 11h
Read-only Register loaded at line compare (the light
pen flip-flop is not implemented). Effective only in
MDA and Hercules modes or when CR03 bit-7 = 0.
VERTICAL SYNC START REGISTER (CR10)
Read/Write at I/O Address 3B5h/3D5h
Index 10h
Group 4 Protection
D7 D6 D5 D4 D3 D2 D1 D0
V Sync Start
(Lower 8 bits)
This register is used in all modes. This register is
not
readable
in
(Line
MDA/Hercules emulation or when CR03 bit-7=1.
7-0
Vertical Sync Start
The eight low order bits of a 10-bit register.
The 9th and 10th bits are located in the
CRTC Overflow Register. They define the
scan line position at which Vertical Sync
becomes active.
Revision 0.7
VERTICAL SYNC END REGISTER (CR11)
Read/Write at I/O Address 3B5h/3D5h
Index 11h
Group 3 Protection for bits 4 and 5
Group 4 Protection for bits 0-3, 6, and 7
D7 D6 D5 D4 D3 D2 D1 D0
This register is used in all modes. This register is
not readable in MDA/Hercules emulation or when
CR03 bit-7=1.
3-0
4
5
6
Compare
bit-9)
7
53
CRT Controller Registers
V Sync End
V Interrupt Clear
V Interrupt Enable
Select Refresh Type
Protect CRTC (Group 0)
Vertical Sync End
The lower 4 bits of the scan line count that
defines the end of vertical sync.
vertical sync width desired is N lines, then
bits 3-0 of this register = (CR10 + N) AND
0Fh.
Vertical Interrupt Clear
0 Clear vertical interrupt generated on
the IRQ output
1 Normal operation
This bit is cleared by RESET.
Vertical Interrupt Enable
0 Enable vertical interrupt (default)
1 Disable vertical interrupt
This bit is cleared by RESET.
Select Refresh Type
0 3 refresh cycles per scan line
1 5 refresh cycles per scan line
Group Protect 0
This bit is logically ORed with XR15 bit-6
to determine the protection for group 0
registers. This bit is cleared by RESET.
0 Enable writes to CR00-CR07
1 Disable writes to CR00-CR07
CR07 bit-4 (Line Compare bit-9) is not
affected by this bit.
Preliminary 65510
If the