F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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Page 58/154:

UNDERLINE LOCATION REGISTER

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VERTICAL DISPLAY ENABLE END
REGISTER (CR12)
Read/Write at I/O Address 3B5h/3D5h
Index 12h
Group 4 Protection
D7 D6 D5 D4 D3 D2 D1 D0
V Display Enable End
7-0
Vertical Display Enable End
These are the eight low order bits of a 10-bit
register. The 9th and 10th bits are located in
the CRT Controller Overflow register. The
actual count = Contents of this register + 1.
OFFSET REGISTER (CR13)
Read/Write at I/O Address 3B5h/3D5h
Index 13h
Group 3 Protection
D7 D6 D5 D4 D3 D2 D1 D0
Display Buffer Width
7-0
Display Buffer Width. The byte starting
address of the next display row = Byte Start
Address for current row + K* (CR13 +
Z/2), where Z = bit defined in XR0D, K = 2
in byte mode, and K = 4 in word mode.
Byte, word and double word mode is
selected by bit-6 of CR17 and bit-6 of
CR14. A less significant bit than bit-0 of
this register is defined in the Auxiliary Off-
set register (XR0D).
resolution of the bit map width. Byte, word
and doubleword mode affects the translation
of the 'logical' display memory address to
the 'physical' display memory address.
Revision 0.7
UNDERLINE LOCATION REGISTER (CR14)
Read/Write at I/O Address 3B5h/3D5h
Index 14h
Group 3 Protection
D7 D6 D5 D4 D3 D2 D1 D0
(Lower 8 bits)
4-0
5
6
7
This allows finer
54
CRT Controller Registers
Underline Position
Count by 4
Doubleword Mode
Reserved
Underline Position
These bits specify the underline's scan line
position within a character row.
Programmed Value = Actual scan line
number – 1
Count by 4 for Doubleword Mode
0 Frame Buffer Address is incremented
by 1 or 2
1 Frame Buffer Address is incremented
by 4 or 2
See CR17 bit-3 for further details.
Doubleword Mode
0 Frame Buffer Address is byte or word
address
1 Frame Buffer Address is doubleword
address
This bit is used in conjunction with CR17
bit-6
to
select
the
display
addressing mode.
Reserved (0)
Preliminary 65510
memory