F65510

Manufacturer Part NumberF65510
DescriptionControllers, Flat Panel VGA Controller
ManufacturerIntel Corporation
F65510 datasheet
 


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®
CRT MODE CONTROL REGISTER (CR17)
Read/Write at I/O Address 3B5h/3D5h
Index 17h
Group 3 Protection for bits 0, 1, and 3-7
Group 4 Protection for bit 2
D7 D6 D5 D4 D3 D2 D1 D0
Compatibility Mode
Select Row Scan Ctr
Vsync Select
Count by 2
Reserved
Address Wrap
Word/Byte Mode
CRTC Reset
0
Compatibility Mode Support
This bit allows compatibility with the IBM
CGA two-bank graphics mode.
0 Character row scan line counter bit 0
is substituted for memory address bit
13 during active display time
1 Normal operation, no substitution
takes place
1
Select Row Scan Counter
This bit allows compatibility with Hercules
graphics and with any other 4-bank graphics
system.
0 Character row scan line counter bit 1
is substituted for memory address bit
14 during active display time
1 Normal operation, no substitution
takes place
2
Vertical Sync Select
This bit controls the vertical resolution of the
CRT Controller by permitting selection of
the clock rate input to the vertical counters.
When set to 1, the vertical counters are
clocked by the horizontal retrace clock
divided by 2.
Revision 0.7
CRT Controller Registers
3
Count By Two
0 Memory
incremented every character clock
1 Memory
incremented every two character
clocks, used in conjunction with bit 5
of 0Fh.
Note: This bit is used in conjunction with
CR14 bit-5. The net effect is as follows:
CR14
CR17
Bit-5
Bit-3
0
0
0
1
1
0
1
1
Note: In Hercules graphics and Hi-res CGA
modes, address inrements every two clocks.
4
Reserved (0)
5
Address Wrap (effective only in word
mode)
0 Wrap display memory address at 16
Kbytes. Used in IBM CGA mode.
1 Normal operation (extended mode).
6
Word Mode or Byte Mode
0 Select Word Mode. In this mode the
display memory address counter bits
are shifted down by one, causing the
most-significant bit of the counter to
appear on the least-significant bit of
the display memory address output
1 Select byte mode
Note: This bit is used in conjunction with
CR14 bit-6 to select byte, word, or double
word memory addressing as follows:
CR14
CR17
Bit-6
Bit-6
0
0
0
1
1
0
1
1
Display memory addresses are affected as
shown in the table on the following page.
7
Hardware Reset
0 Force HSYNC and VSYNC inactive.
No other registers or outputs affected.
1 Normal Operation
This bit is cleared by RESET.
56
address
counter
is
address
counter
is
Increment
Addressing
Every
1 CCLK
2 CCLK
4 CCLK
2 CCLK
Addressing Mode
Word Mode
Byte Mode
Double Word Mode
Double Word Mode
Preliminary 65510